1. 1 Temperature-Aware Resource Allocation and Binding in High Level Synthesis Authors: Rajarshi Mukherjee, Seda Ogrenci Memik, and Gokhan Memik Presented by: Nivya Papakannu ECE Department, UMASS Amherst

2. 2 Overview: Introduction Temperature-Aware High Level Synthesis –Temperature Model and Assumptions –Resource Allocation and Binding Experimental Setup & Results Conclusions

3. 3 Introduction: Continuous technology scaling following Moore’s Law Billion transistor IC Massive computational power Increase in power density –Increase in temperature One of the biggest challenges in VLSI design

4. 4 Need for thermal Awareness: Functional Incorrectness –Carrier mobility decrease –Interconnect resistance increase Reliability Issues –Electro-migration –Transient and Permanent faults Thermal Considerations –10  C rise – component failure rate doubles Non-uniform distribution –“HOTSPOTS ” Leakage Power –Dominant in current technologies –Increasing with future technologies –Exponential dependence on temperature Higher Temperature  Higher PowerHigher Temperature  Higher Power

5. 5 Thermal Awareness in HLS: Can we prevent high temperatures in the first place? Will power optimization help? –Not always –No individual consideration Incorporate physical phenomenon in all stages of design flow –Thermal driven floor planning and placement –Thermal Aware High Level Synthesis

6. 6 Temperature Model & Leakage Model: Thermal Model –Analogy between heat transfer and RC circuits  T tot is the temperature contribution due to power dissipation –P tot = P switch + P leakage –  t = one clock cycle duration Temperature Variation –Modeled as exponential transient behavior analogous to electrical time constant RC –R : thermal resistance, C: thermal capacitance Leakage Model Leakage has exponential dependence –Threshold voltage V th –Temperature T 4 th order polynomial to represent P leakage At 180nm –15% of dynamic power at ambient temperature –Doubles every 25  C

7. 7 Temperature Aware Resource Allocation and Binding: Scheduled Data Flow Graph –Allocation and Binding Compatibility graph for each operation type –Operations are vertices –Edges labeled with switched capacitance Two Modes for optimizing temperature –Temperature constrained resource minimization (TC) –Resource constrained temperature minimization (RC)

8. 8 DFG & Compatibility Graph: For k resources – finds k paths s.t. sum of edge weights is min. 1+ 2+ 3+ 4+5+ 1+2+ 3+ 4+ 5+ 6+ 1 2 3 4 Data Flow Graph Compatibility Graph R1R2

9. 9 Relaxation: Relaxation –Determine the predecessor or parent of each vertex –Relaxation idea based on Dijkstra’s shortest path algorithm –For each vertex the best parent is determined through which we could reach the vertex by relaxing the vertices based on the constraint criteria. Temperature Constrained (TC) –Relax vertices that do not violate temperature constraint Resource Constrained (RC) –Relax vertex with minimum rise in temperature.

10. 10 Temperature Aware Resource Allocation and Binding Determine the parent of each vertex –Relaxation sw ab sw bc sw de sw ef sw fg gfedcb sw cd a

11. 11 Temperature Constrained Resource Allocation and Binding Determine the parent of each vertex –Relaxation sw ab sw bc sw de sw ef sw fg gfedcb sw cd a

12. 12 Temperature Constrained Resource Allocation and Binding Determine the parent of each vertex –Relaxation sw ab sw bc sw de sw ef sw fg gfedcb sw cd a T1T1 a Candidates Temperature of R1 TaTa

13. 13 Temperature Constrained Resource Allocation and Binding Determine the parent of each vertex –Relaxation sw ab T2T2 sw bc sw de sw ef sw fg gfedcb sw cd a T2T2 T2T2 T2T2 T2T2 T2T2  (a) abac ag Temperature of R1 T ab T ac T ag T1T1 Candidates

14. 14 Temperature Constrained Resource Allocation and Binding Determine the parent of each vertex –Relaxation sw ab T2T2 sw bc sw de sw ef sw fg gfedcb sw cd a T2T2 T3T3 T3T3 T2T2 T3T3  (a)  (b)  (a)  (b) abacdabe abc X Temperature of R1 T abd T abe T ac T1T1 Candidates

15. 15 Temperature Constrained Resource Allocation and Binding Determine the parent of each vertex –Relaxation sw ab T2T2 sw bc sw de sw ef sw fg gfedcb sw cd a T2T2 T3T3 T3T3 T2T2 T4T4  (a)  (b)  (a)  (d) abde abdg X T1T1 Candidates Temperature of R1 T abdg abe T abe ac T ac

16. 16 Temperature Constrained Resource Allocation and Binding Determine the parent of each vertex –Relaxation –Select the longest path –Bind to a resource –Shown for temperature constrained binding sw ab T2T2 gfedcba T2T2 T3T3 T3T3 T2T2 T4T4  (a)  (b)  (a)  (d) Resource 1 sw dg sw bd abdg R1 T1T1

17. 17 Resource Constrained Allocation and Binding Determine the parent of each vertex –Relaxation sw ab sw bc sw de sw ef sw fg gfedcb sw cd a a T1T1 TaTa Temperature on R1 Candidate

18. 18 Resource Constrained Allocation and Binding Determine the parent of each vertex –Relaxation sw ab T2T2 sw bc sw de sw ef sw fg gfedcb sw cd a  (a) T1T1 T ab ab Temperature on R1 Candidate

19. 19 Resource Constrained Allocation and Binding Determine the parent of each vertex –Relaxation sw ab T2T2 sw bc sw de sw ef sw fg gfedcb sw cd a T3T3  (a) ab  (b) d T1T1 Temperature on R1 T abd Candidate

20. 20 Resource Constrained Allocation and Binding Determine the parent of each vertex –Relaxation sw ab T2T2 sw bc sw de sw ef sw fg gfedcb sw cd a T3T3 T4T4  (a) ab R1  (b) d  (d) f T1T1 Temperature on R1 T abdf Candidate

21. 21 Resource Constrained Allocation and Binding Determine the parent of each vertex –Relaxation sw ab T2T2 sw bc sw de sw ef sw fg gfedcb sw cd a T3T3 T4T4 T5T5  (a) ab R1  (b) d  (d) f  (f) g T1T1 Temperature on R1 T abdfg Candidate

22. 22 Resource Constrained Allocation and Binding Determine the parent of each vertex –Relaxation –Returns the longest path –Bind to a resource –Shown for resource constrained binding sw ab gfedcba  (a)  (b)  (d)  (f) Resource 1 sw fd sw bd ab R1 dfg sw fg T2T2 T3T3 T4T4 T5T5 T1T1

23. 23 Temperature Aware Resource Allocation and Binding Determine the parent of each vertex –Relaxation –Select the longest path –Bind to operations a resource –Remove operations from comparability graph –Build new comparability graph –Continue until all operations are bound to a resource sw ef fec sw ce

24. 24 Temperature Aware Resource Allocation and Binding Successive paths from relaxation represent binding of the operations to a new resource Post-Processing –Merging/dividing resources sw ab T i+1 sw ef gfedcba T i+1  (a)  (c)  (d) Resource 1 Resource 2 sw dg sw bd sw cf  (b) abdg cf R1 R2

25. 25 Experimental Flow: Applications in C SUIF Scheduler DFGs of Popular DSP Algorithms Min-Cost Flow Binding Temperature-Aware Allocation & Binding Min Resource Binding under TC Binding with optimal switching Min Temperature Binding under RC Temperature-Aware Binding DFGs RC TC Synopsys DC for Capacitance Extraction ModelSim Simulation for Switching Activity Compare with low power binding

26. 26 Resource Overhead BenchmarksSW_OPT [MUL, ALU] TC_R_MIN [MUL, ALU] ewf3, 54, 8 arf4, 25, 4 jctrans_12, 32, 7 jctrans_20, 40, 6 jdmerge13, 63, 7 jdmerge23, 63, 9 jdmerge33, 63, 9 jdmerge43, 55, 9 motion_24, 66, 8 motion_34, 66, 8 noise_est_23, 44, 7 28% increase in MULs 54% increase in ALUs

27. 27 Experimental Results – Temperature Maximum Temperature Reached by ALUs 11.9  C 3.6  C 19.2  C11.2  C

28. 28 Experimental Results – Temperature Maximum Temperature Reached by Multipliers 7.6  C2.7  C 10.3  C 18.9  C

29. 29 Experimental Results – Leakage Power Normalized leakage power consumption of the three techniques at 180nm 9% 2% 2.18

30. 30 Experimental Results – Total Power Normalized total power consumption of the three techniques at 180nm 34% 5% 2.38

31. 31 Conclusions: Introduced Resource binding Techniques to create temperature-awareness in HLS Temperature-aware resource allocation and binding Effectively minimized the maximum temperature reached by a module –Temperature constrained –Resource constrained Leakage and total power savings in future technologies A reliability driven methodology can leverage on this mechanism to prevent or reduce likelihood of hotspots on a chip