1. Aug. 13, 2005Mudlapur et al.: VDAT'051 A Novel Random Access Scan Flip-Flop Design Anand S. Mudlapur Vishwani D. Agrawal (Speaker) Adit D. Singh Department of Electrical and Computer Engineering Auburn University, AL 36849, USA Ninth VLSI Design and Test Symposium – VDAT ’05 Bangalore, 10-13, 2005

2. Aug. 13, 2005Mudlapur et al.: VDAT'052 Motivation for This Work Conventional serial scan (SS) test sequences are increasing rapidly to an unimaginable quantity leading to long test time. Scan-in and scan-out result in high switching activity during test. Reduction of power and test time are complimentary objectives in serial scan.

3. Aug. 13, 2005Mudlapur et al.: VDAT'053 Outline Introduction The RAS solution and a unique “toggle” Flip-Flop design Advantage of our design in eliminating two global signals Results on ISCAS Benchmark Circuits Conclusion

4. Aug. 13, 2005Mudlapur et al.: VDAT'054 Introduction Random Access Scan (RAS) offers a single solution to the problems faced by serial scan (SS): –Each RAS cell is uniquely addressable for read or write. –RAS reduces test application time and test power which are otherwise complimentary objectives. Publications on RAS: Ando, COMPCON -80 Wagner, COMPCON -83 Baik et al., VLSI Design -04 Mudlapur et al., ITC -05 Disadvantage: High routing overhead – test control, address and scan-in signals must be routed to all flip-flops.

5. Aug. 13, 2005Mudlapur et al.: VDAT'055 Serial Scan (SS) Example:Consider a circuit with 5,000 FFs and 10,000 combinational test vectors Total test cycles = 5,000 x 10,000 + 10,000 + 5,000 50,015,000 = 50,015,000 Combinational Circuit FF Scan-inScan-out PIPO Test control (TC)

6. Aug. 13, 2005Mudlapur et al.: VDAT'056 Random Access Scan (RAS) During every test, only a subset of all Flip-flops needs to be set and observed for targeted faults Combinational Circuit FF PIPO Scan-out bus bus Decoder AddressInputs Scan-in TC These signals are eliminated in our design

7. Aug. 13, 2005Mudlapur et al.: VDAT'057 The “Toggle” RAS Flip-Flop MS Clock MUXMUX Combinational Logic Data Row Decoder Column Decoder To Combinational Logic To Scan-out Bus Address (log 2 n ff ) y x √n ff Lines RAS-FF Decoded address lines

8. Aug. 13, 2005Mudlapur et al.: VDAT'058 Toggle Flip-Flop Operation FunctionClock Address decoder outputs Row (x)Column (y) Normal DataActive00 Toggle Data Inactive1Active Clock InactiveActive Clock1 Hold Data Inactive10 01 00

9. Aug. 13, 2005Mudlapur et al.: VDAT'059 Toggle Flip-Flop Operation (contd.) RAS FF 0 RAS FF 1 RAS FF 1 Unaddressed FFs Addressed FF RAS FF 0 Decoded address lines

10. Aug. 13, 2005Mudlapur et al.: VDAT'0510 Macro Level Idea of Signals to RAS-FF RAS FF11 D-FF x1 x2 x3 x4 y1y2y3y4 RAS FF12 RAS FF13 RAS FF14 RAS FF24 RAS FF23 RAS FF22 RAS FF21 RAS FF34 RAS FF33 RAS FF32 RAS FF31 RAS FF41 RAS FF42 RAS FF43 RAS FF44 D-FF To Next Level

11. Aug. 13, 2005Mudlapur et al.: VDAT'0511 Gate Area Overhead Gate area overhead of Serial Scan = Gate area overhead of Random Access Scan = n ff – Number of Flip-Flops n g – Number of Gates

12. Aug. 13, 2005Mudlapur et al.: VDAT'0512 Gate Area Overhead (Example) A circuit with 5,120 gates and 512 FFs Gate overhead of serial scan = 20 % Gate overhead of RAS = 30.2 % A circuit with 20,480 gates and 512 FFs Gate overhead of serial scan = 8 % Gate overhead of RAS = 12 %

13. Aug. 13, 2005Mudlapur et al.: VDAT'0513 Overhead in terms of Transistors Gate area overhead of Serial Scan = Gate area overhead of Random Access Scan = Synthesis performed on SUN ULTRA 5 Machine RAS has 16 transistors more than SS Flip-Flop

14. Aug. 13, 2005Mudlapur et al.: VDAT'0514 Results

15. Aug. 13, 2005Mudlapur et al.: VDAT'0515 Results (Contd.)

16. Aug. 13, 2005Mudlapur et al.: VDAT'0516 Conclusion New design of a “Toggle” Flip-Flop reduces the RAS routing overhead. A proposed RAS architecture with new FF has several other advantages: –Algorithmic minimization reduces test cycles by 60%. –Power dissipation during test is reduced by 99%. For details, see Mudlapur et al., ITC-05.