1. Chapter 21 Chapter 2 Algebraic Methods for the Analysis and Synthesis of Logic Circuits

2. Chapter 22 Fundamentals of Boolean Algebra (1) Basic Postulates Postulate 1 (Definition): A Boolean algebra is a closed algebraic system containing a set K of two or more elements and the two operators  and +. Postulate 2 (Existence of 1 and 0 element): (a) a + 0 = a (identity for +),(b) a  1 = a (identity for  ) Postulate 3 (Commutativity): (a) a + b = b + a,(b) a  b = b  a Postulate 4 (Associativity): (a) a + (b + c) = (a + b) + c(b) a  (b  c) = (a  b)  c Postulate 5 (Distributivity): (a) a + (b  c) = (a + b)  (a + c)(b) a  (b + c) = a  b + a  c Postulate 6 (Existence of complement): (a) (b) Normally  is omitted.

3. Chapter 23 Fundamentals of Boolean Algebra (2) Fundamental Theorems of Boolean Algebra Theorem 1 (Idempotency): (a) a + a = a(b) aa = a Theorem 2 (Null element): (a) a + 1 = 1(b) a0 = 0 Theorem 3 (Involution) Properties of 0 and 1 elements (Table 2.1): ORANDComplement a + 0 = 0a0 = 00' = 1 a + 1 = 1a1 = a1' = 0

4. Chapter 24 Fundamentals of Boolean Algebra (3) Theorem 4 (Absorption) (a) a + ab = a(b) a(a + b) = a Examples: –(X + Y) + (X + Y)Z = X + Y[T4(a)] –AB'(AB' + B'C) = AB'[T4(b)] Theorem 5 (a) a + a'b = a + b(b) a(a' + b) = ab Examples: –B + AB'C'D = B + AC'D[T5(a)] –(X + Y)((X + Y)' + Z) = (X + Y)Z[T5(b)]

5. Chapter 25 Fundamentals of Boolean Algebra (4) Theorem 6 (a) ab + ab' = a(b) (a + b)(a + b') = a Examples: –ABC + AB'C = AC[T6(a)] –(W' + X' + Y' + Z')(W' + X' + Y' + Z)(W' + X' + Y + Z')(W' + X' + Y + Z) = (W' + X' + Y')(W' + X' + Y + Z')(W' + X' + Y + Z)[T6(b)] = (W' + X' + Y')(W' + X' + Y)[T6(b)] = (W' + X')[T6(b)]

6. Chapter 26 Fundamentals of Boolean Algebra (5) Theorem 7 (a) ab + ab'c = ab + ac(b) (a + b)(a + b' + c) = (a + b)(a + c) Examples: –wy' + wx'y + wxyz + wxz' = wy' + wx'y + wxy + wxz'[T7(a)] = wy' + wy + wxz'[T7(a)] = w + wxz'[T7(a)] = w[T7(a)] –(x'y' + z)(w + x'y' + z') = (x'y' + z)(w + x'y')[T7(b)]

7. Chapter 27 Fundamentals of Boolean Algebra (6) Theorem 8 (DeMorgan's Theorem) (a) (a + b)' = a'b'(b) (ab)' = a' + b' Generalized DeMorgan's Theorem (a) (a + b + … z)' = a'b' … z'(b) (ab … z)' = a' + b' + … z' Examples: –(a + bc)'= (a + (bc))' = a'(bc)'[T8(a)] = a'(b' + c')[T8(b)] = a'b' + a'c'[P5(b)] –Note: (a + bc)'  a'b' + c'

8. Chapter 28 Fundamentals of Boolean Algebra (7) More Examples for DeMorgan's Theorem –(a(b + z(x + a')))' = a' + (b + z(x + a'))'[T8(b)] = a' + b' (z(x + a'))'[T8(a)] = a' + b' (z' + (x + a')')[T8(b)] = a' + b' (z' + x'(a')')[T8(a)] = a' + b' (z' + x'a)[T3] = a' + b' (z' + x')[T5(a)] –(a(b + c) + a'b)'= (ab + ac + a'b)'[P5(b)] = (b + ac)'[T6(a)] = b'(ac)'[T8(a)] = b'(a' + c')[T8(b)]

9. Chapter 29 Fundamentals of Boolean Algebra (8) Theorem 9 (Consensus) (a) ab + a'c + bc = ab + a'c (b) (a + b)(a' + c)(b + c) = (a + b)(a' + c) Examples: –AB + A'CD + BCD = AB + A'CD[T9(a)] –(a + b')(a' + c)(b' + c) = (a + b')(a' + c)[T9(b)] –ABC + A'D + B'D + CD = ABC + (A' + B')D + CD[P5(b)] = ABC + (AB)'D + CD[T8(b)] = ABC + (AB)'D[T9(a)] = ABC + (A' + B')D[T8(b)] = ABC + A'D + B'D[P5(b)]

10. Chapter 210 Switching Functions Switching algebra: Boolean algebra with the set of elements K = {0, 1} If there are n variables, we can define switching functions. Sixteen functions of two variables (Table 2.3): A switching function can be represented by a table as above, or by a switching expression as follows: f 0 (A,B)= 0, f 6 (A,B) = AB' + A'B, f 11 (A,B) = AB + A'B + A'B' = A' + B,... Value of a function can be obtained by plugging in the values of all variables: The value of f 6 when A = 1 and B = 0 is: = 0 + 1 = 1.

11. Chapter 211 Truth Tables (1) Shows the value of a function for all possible input combinations. Truth tables for OR, AND, and NOT (Table 2.4):

12. Chapter 212 Truth Tables (2) Truth tables for f(A,B,C) = AB + A'C + AC' (Table 2.5)

13. Chapter 213 Algebraic Forms of Switching Functions (1) Literal: A variable, complemented or uncomplemented. Product term: A literal or literals ANDed together. Sum term: A literal or literals ORed together. SOP (Sum of Products): ORing product terms f(A, B, C) = ABC + A'C + B'C POS (Product of Sums) ANDing sum terms f (A, B, C) = (A' + B' + C')(A + C')(B + C')

14. Chapter 214 Algebraic Forms of Switching Functions (2) A minterm is a product term in which all the variables appear exactly once either complemented or uncomplemented. Canonical Sum of Products (canonical SOP): –Represented as a sum of minterms only. –Example: f 1 (A,B,C) = A'BC' + ABC' + A'BC + ABC(2.1) Minterms of three variables:

15. Chapter 215 Algebraic Forms of Switching Functions (3) Compact form of canonical SOP form: f 1 (A,B,C) = m2 + m3 + m 6 + m 7 (2.2) A further simplified form: f 1 (A,B,C) =  m (2,3,6,7) (minterm list form)(2.3) The order of variables in the functional notation is important. Deriving truth table of f 1 (A,B,C) from minterm list:

16. Chapter 216 Algebraic Forms of Switching Functions (4) Example: Given f(A,B,Q,Z) = A'B'Q'Z' + A'B'Q'Z + A'BQZ' + A'BQZ, express f(A,B,Q,Z) and f '(A,B,Q,Z) in minterm list form. f(A,B,Q,Z)= A'B'Q'Z' + A'B'Q'Z + A'BQZ' + A'BQZ = m 0 + m 1 + m 6 + m 7 =  m(0, 1, 6, 7) f '(A,B,Q,Z)= m 2 + m 3 + m 4 + m 5 + m 8 + m 9 + m 10 + m 11 + m 12 + m 13 + m 14 + m 15 =  m(2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15) (2.6) AB + (AB)' = 1 and AB + A' + B' = 1, but AB + A'B'  1.

17. Chapter 217 Algebraic Forms of Switching Functions (5) A maxterm is a sum term in which all the variables appear exactly once either complemented or uncomplemented. Canonical Product of Sums (canonical POS): –Represented as a product of maxterms only. –Example: f 2 (A,B,C) = (A+B+C)(A+B+C')(A'+B+C)(A'+B+C') (2.7) Maxterms of three variables:

18. Chapter 218 Algebraic Forms of Switching Functions (6) f 2 (A,B,C) = M 0 M 1 M 4 M 5 (2.8) =  M(0,1,4,5) (maxterm list form)(2.9) The truth table for f 2 (A,B,C):

19. Chapter 219 Algebraic Forms of Switching Functions (7) Truth tables of f 1 (A,B,C) of Eq. (2.3) and f 2 (A,B,C) of Eq. (2.7) are identical. Hence, f 1 (A,B,C) =  m (2,3,6,7) = f 2 (A,B,C) =  M(0,1,4,5) (2.10) Example: Given f(A,B,C) = ( A+B+C')(A+B'+C')(A'+B+C')(A'+B'+C'), construct the truth table and express in both maxterm and minterm form. –f(A,B,C) = M 1 M 3 M 5 M 7 =  M(1,3,5,7) =  m (0,2,4,6)

20. Chapter 220 Algebraic Forms of Switching Functions (8) Relationship between minterm m i and maxterm M i : –For f(A,B,C), (m 1 )' = (A'B'C)' = A + B + C' = M 1 –In general, (m i )' = M i (2.11) (Mi)' = ((m i )')' = m i (2.12)

21. Chapter 221 Algebraic Forms of Switching Functions (9) Example: Relationship between the maxterms for a function and its complement. –For f(A,B,C) = ( A+B+C')(A+B'+C')(A'+B+C')(A'+B'+C') –The truth table is:

22. Chapter 222 Algebraic Forms of Switching Functions (10) –From the truth table f '(A,B,C) =  M(0,2,4,6) and f(A,B,C) =  M(1,3,5,7) –Since f(A,B,C)  f '(A,B,C) = 0, (M 0 M 2 M 4 M 6 )(M 1 M 3 M 5 M 7 ) = 0 or –In general, (2.13) –Another observation from the truth table: f(A,B,C) =  m (0,2,4,6) =  M(1,3,5,7) f '(A,B,C) =  m (1,3,5,7) =  M(0,2,4,6)

23. Chapter 223 Derivation of Canonical Forms (1) Derive canonical POS or SOP using switching algebra. Theorem 10. Shannon's expansion theorem (a). f(x 1, x 2, …, x n ) = x 1 f(1, x 2, …, x n ) + (x 1 )' f(0, x 2, …, x n ) (b). f(x 1, x 2, …, x n ) = [x 1 + f(0, x 2, …, x n )] [(x 1 )' + f(1, x 2, …, x n )] Example: f(A,B,C) = AB + AC' + A'C –f(A,B,C) = AB + AC' + A'C = A f(1,B,C) + A' f(0,B,C) = A(1  B + 1  C' + 1'  C) + A'(0  B + 0  C' + 0'  C) = A(B + C') + A'C –f(A,B,C) = A(B + C') + A'C = B[A(1+C') + A'C] + B'[A(0 + C') + A'C] = B[A + A'C] + B'[AC' + A'C] = AB + A'BC + AB'C' + A'B'C –f(A,B,C) = AB + A'BC + AB'C' + A'B'C = C[AB + A'B  1 + AB'  1' + A'B'  1] + C'[AB + A'B  0 + AB'  0' + A'B'  0] = ABC + A'BC + A'B'C + ABC' + AB'C'

24. Chapter 224 Derivation of Canonical Forms (2) Alternative: Use Theorem 6 to add missing literals. Example: f(A,B,C) = AB + AC' + A'C to canonical SOP form. –AB = ABC' + ABC = m 6 + m 7 –AC' = AB'C' + ABC' = m 4 + m 6 –A'C = A'B'C + A'BC = m 1 + m 3 –Therefore, f(A,B,C) = (m 6 + m 7 ) + (m 4 + m 6 ) + (m 1 + m 3 ) =  m(1, 3, 4, 6, 7) Example: f(A,B,C) = A(A + C') to canonical POS form. –A = (A+B')(A+B) = (A+B'+C')(A+B'+C)(A+B+C')(A+B+C) = M 3 M 2 M 1 M 0 –(A+C')= (A+B'+C')(A+B+C') = M 3 M 1 –Therefore, f(A,B,C) = (M 3 M 2 M 1 M 0 )(M 3 M 1 ) =  M(0, 1, 2, 3)

25. Chapter 225 Incompletely Specified Functions A switching function may be incompletely specified. Some minterms are omitted, which are called don't-care minterms. Don't cares arise in two ways: –Certain input combinations never occur. –Output is required to be 1 or 0 only for certain combinations. Don't care minterms: d i Don't care maxterms: D i Example: f(A,B,C) has minterms m 0, m 3, and m 7 and don't-cares d 4 and d 5. –Minterm list is: f(A,B,C) =  m(0,3,7) + d(4,5) –Maxterm list is: f(A,B,C) =  M(1,2,6)·D(4,5) –f '(A,B,C) =  m(1,2,6) + d(4,5) =  M(0,3,7)·D(4,5) –f (A,B,C)= A'B'C' + A'BC + ABC + d(AB'C' + AB'C) = B'C' + BC (use d 4 and omit d 5 )

26. Chapter 226 Electronic Logic Gates (1) Electrical Signals and Logic Values –A signal that is set to logic 1 is said to be asserted, active, or true. –An active-high signal is asserted when it is high (positive logic). –An active-low signal is asserted when it is low (negative logic).

27. Chapter 227 Electronic Logic Gates (2)

28. Chapter 228 Electronic Logic Gates (3)

29. Chapter 229 Electronic Logic Gates (4)

30. Chapter 230 Electronic Logic Gates (5)

31. Chapter 231 Basic Functional Components (1) AND (a) AND logic function. (b) Electronic AND gate. (c) Standard symbol. (d) IEEE block symbol.

32. Chapter 232 Basic Functional Components (2) OR (a) OR logic function. (b) Electronic OR gate. (c) Standard symbol. (d) IEEE block symbol.

33. Chapter 233 Basic Functional Components (3) Meaning of the designation  1 in IEEE symbol:

34. Chapter 234 Basic Functional Components (4) NOT (a) NOT logic function. (b) Electronic NOT gate. (c) Standard symbol. (d) IEEE block symbol.

35. Chapter 235 Basic Functional Components (5) Positive Versus Negative Logic

36. Chapter 236 Basic Functional Components (6) AND Gate Usage in Negative Logic –(a) AND gate truth table (L = 1, H = 0) –(b) Alternate AND gate symbol (in negative logic) –(c) Preferred usage –(d) Improper usage –y = a·b = (2.14) – (2.15)

37. Chapter 237 Basic Functional Components (7) OR Gate Usage in Negative Logic –(a) OR gate truth table(L = 1, H = 0) –(b) Alternate OR gate symbol (in negative logic) –(c) Preferred usage –(d) Improper usage – (2.16) – (2.17)

38. Chapter 238 Basic Functional Components (8) Example 2.32: Building smoke alarm system –Components: two smoke detectors, a sprinkler, and an automatic telephone dialer –Behavior: Sprinkler is activated if either smoke detector detects smoke. When both smoke detector detect smoke, fire department is called. –Signals: : Active-low outputs from two smoke detectors. : Active-low input to the sprinkler : Active-low input to the telephone dialer. –Logic equations (2.18) (2.19)

39. Chapter 239 Basic Functional Components (9) Logic diagram of the smoke alarm system

40. Chapter 240 Basic Functional Components (10) NAND –(a) NAND logic function –(b) Electronic NAND gate –(c) Standard symbol –(d) IEEE block symbol

41. Chapter 241 Basic Functional Components (10) Matching signal polarity to NAND gate inputs/outputs – (a) Preferred usage (b) Improper usage Additional properties of NAND gate: Hence, NAND gate may be used to implement all three elementary operators.

42. Chapter 242 Basic Functional Components (11) AND, OR, and NOT gates constructed exclusively from NAND gates

43. Chapter 243 Basic Functional Components (12) NOR –(a) NAND logic function –(b) Electronic NAND gate –(c) Standard symbol –(d) IEEE block symbol

44. Chapter 244 Basic Functional Components (13) Matching signal polarity to NOR gate inputs/outputs – (a) Preferred usage (b) Improper usage Additional properties of NAND gate: Hence, NAND gate may be used to implement all three elementary operators.

45. Chapter 245 Basic Functional Components (14) AND, OR, and NOT gates constructed exclusively from NOR gates.

46. Chapter 246 Basic Functional Components (15) Exclusive-OR (XOR) –f XOR (a, b) = a  b = (2.24) (a) XOR logic function (b) Electronic XOR gate (c) Standard symbol (d) IEEE block symbol

47. Chapter 247 Basic Functional Components (16) POS of XOR a  b [P2(a), P6(b)] [P5(b)] Some other useful relationships –a  a = 0(2.25) –a  = 1(2.26) –a  0 = a (2.27) –a  1 = (2.28) – (2.29) –a  b = b  a(2.30) –a  (b  c) = (a  b)  c(2.31)

48. Chapter 248 Basic Functional Components (17) Output of XOR gate is asserted when the mathematical sum of inputs is one: The output of XOR is the modulo-2 sum of its inputs.

49. Chapter 249 Basic Functional Components (18) Exclusive-NOR (XNOR) –f XNOR (a, b) = a b(2.32) –(a) XNOR logic function –(b) Electronic XNOR gate –(c) Standard symbol –(d) IEEE block symbol

50. Chapter 250 Basic Functional Components (19) SOP and POS of XNOR a b [P2] [T8(a)] [T8(b)] [P5(b)] [P6(b), P2(a)] = a b

51. Chapter 251 Analysis of Combinational Circuits (1) Digital Circuit Design: –Word description of a function  a set of switching equations  hardware realization (gates, programmable logic devices, etc.) Digital Circuit Analysis: –Hardware realization  switching expressions, truth tables, timing diagrams, etc. Analysis is used –To determine the behavior of the circuit –To verify the correctness of the circuit –To assist in converting the circuit to a different form.

52. Chapter 252 Analysis of Combinational Circuits (2) Algebraic Method: Use switching algebra to derive a desired form. Example 2.33: Find a simplified switching expressions and logic network for the following logic circuit (Fig. 2.21a).

53. Chapter 253 Analysis of Combinational Circuits (3) Write switching expression for each gate output: – The output is: Simplify the output function using switching algebra: [Eq. 2.24] [T8] [T5(b)] [T4(a)] = b c[Eq. 2.32] Therefore, f (a,b,c) = (b c)' =

54. Chapter 254 Analysis of Combinational Circuits (4) Example 2.34: Find a simplified switching expressions and logic network for the following logic circuit (Fig. 2.22).

55. Chapter 255 Analysis of Combinational Circuits (5) Derive the output expression: f(a,b,c) = =[T8(b)] =[T8(a)] =[Eq. 2.24] =[P5(b)] = [P6(b), T4(a)] =[T4(a)] =[T9(a)] =[T7(a)] =[Eq. 2.24]

56. Chapter 256 Analysis of Combinational Circuits (6) Truth Table Method: Derive the truth table one gate at a time. The truth table for Example 2.34:

57. Chapter 257 Analysis of Combinational Circuits (7) Analysis of Timing Diagrams –Timing diagram is a graphical representation of input and output signal relationships over the time dimension. –Timing diagrams may show intermediate signals and propagation delays.

58. Chapter 258 Analysis of Combinational Circuits (8) Example 2.35: Derivation of truth table from a timing diagram

59. Chapter 259 Analysis of Combinational Circuits (9) Propagation Delay –Physical characteristics of a logic circuit to be considered: Propagation delays Gate fan-in and fan-out restrictions Power consumption Size and weight –Propagation delay: The delay between the time of an input change and the corresponding output change. –Typical two propagation delay parameters: t PLH = propagation delay time, low-to-high-level output t PHL = propagation delay time, high-to-low-level output –Approximation:

60. Chapter 260 Analysis of Combinational Circuits (10) Propagation delay through a logic gate

61. Chapter 261 Analysis of Combinational Circuits (11) Power dissipation and propagation delays for several logic families (Table 2.7)

62. Chapter 262 Analysis of Combinational Circuits (12) Propagation delays of primitive 74LS series gates (Table 2.8)

63. Chapter 263 Analysis of Combinational Circuits (13) Example 2.36: Given a circuit diagram and the timing diagram, find the truth table and minimum switching expression.

64. Chapter 264 Synthesis of Combinational Logic Circuits (1) AND-OR and NAND Networks –Switching expression must be in SOP form. –Example: – [T3] [T8(a)] where and

65. Chapter 265 Synthesis of Combinational Logic Circuits (2) OR-AND and NOR Networks –Switching expression must be in POS form. –Example: – [T3] [T8(b)] where and

66. Chapter 266 Synthesis of Combinational Logic Circuits (3) Two-level Circuits –Input signals pass through two levels of gates before reaching the output. –Implementation procedure for NAND (NOR) logic: Step 1. Express the function in minterm (maxterm) list form. Step 2. Write out the minterms (maxterms) in algebraic form. Step 3. Simplify the function in SOP (POS) form. Step 4. Transform the expression into the NAND (NOR) form. Step 5. Draw the NAND (NOR) logic diagram.

67. Chapter 267 Synthesis of Combinational Logic Circuits (4) Circuits with more than two levels are often needed due to fan-in constraints.

68. Chapter 268 Synthesis of Combinational Logic Circuits (5) Example 2.37: NAND implementation of f  (X,Y,Z) =  m(0,3,4,5,7) 1. f  (X,Y,Z) =  m(0,3,4,5,7) 2. f  (X,Y,Z) = m 0 + m 3 + m 4 + m 5 + m 7 3. [T6(a)] 4a. [T4] or 4b. [T3] [T8(a)]

69. Chapter 269 Synthesis of Combinational Logic Circuits (6) AND-OR-invert Circuits –A set of AND gates followed by a NOR gate. –Used to readily realize two-level SOP circuits. –7454 circuit:

70. Chapter 270 Synthesis of Combinational Logic Circuits (7) Factoring –A technique to obtain higher-level forms of switching functions. –Higher-level forms: May need less hardware May be used when there are fan-in constraints More difficult to design Slower Example 2.39:

71. Chapter 271 Synthesis of Combinational Logic Circuits (8) Example 2.40: f (a,b,c,d) =  m(8,13) with only two-input AND and OR gates. –Write the canonical SOP form: f (a,b,c,d) =  m(8,13) = (2.34) Two four-input AND gates and one two-input OR gate are needed. –Apply factoring: (2.35)

72. Chapter 272 Synthesis of Combinational Logic Circuits (9) Example 2.41: A burglar alarm with four control switches, each of which produces logic 1 when: Switch A: Secret switch is closed Switch B: Safe is in its normal position in the closet Switch C: Clock is between 1000 and 1400 hours Switch D: Closet door is closed. Write the equations of the control logic that produces logic 1 when the safe is moved AND the secret switch is closed, OR the closet is opened after banking hours, OR the closet is opened with the control switch open.

73. Chapter 273 Synthesis of Combinational Logic Circuits (10) Example 2.42: The Doe family voter: –Vote for either hamburgers (0) or chicken (1). –Majority wins. –If Mom and Dad agree, they win. –John (Dad): A, Jane (Mom):B, Joe: C, Sue: D. –The logic function is:

74. Chapter 274 Synthesis of Combinational Logic Circuits (11) Example 2.43: Logic equations for a circuit that adds two 2-bit binary numbers (A 1 A 0 ) 2 and (B 1 B 0 ) 2, and produces sum bits (S 1 S 0 ) 2 and carry bit C 1 ; A 1 A 0 + B 1 B 0 C 1 S 1 S 0

75. Chapter 275 Synthesis of Combinational Logic Circuits (12) Truth Table : A1 A0 B1 B0 C1 S1 S0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 1 1 0 1 1 0 1 0 0 0 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 1 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 1 1 1 0 1 0 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 1 0 0 Logic equations: S 0 = S 1 = C 1 =

76. Chapter 276 Synthesis of Combinational Logic Circuits (13) Reduced equations: S 0 = S 1 = C 1 =

77. Chapter 277 Computer-aided Design (1) Design Cycle

78. Chapter 278 Computer-aided Design (2) Digital Circuit Modeling –Purpose of modeling: Helps the designer formalize a solution. To check errors, verify correctness, and predict timing characteristics. –CAD tools are available for design optimization and transformation of design from abstract form to a physical realization. –Model can represent different levels of design abstraction.

79. Chapter 279 Computer-aided Design (3) High-level abstract model (behavioral model) –Describes only desired behavior. –Usually represented using a hardware description language (HDL), e.g., VHDL or Verilog. –Other representation mechanisms: logic equations, truth tables, and minterm or maxterm lists.

80. Chapter 280 Computer-aided Design (4) Behavioral models of a full-adder circuit: (a) block diagram, (b) truth table, (c) logic equations.

81. Chapter 281 Computer-aided Design (5) VHDL behavioral model of a full adder circuit (Figure 2.38) –Entity defines the interface between the circuit and the outside world. –Architecture defines the function implemented within the circuit. –Multiple architectures may be defined for a given entity. Structural model –Interconnection of components. –Behavior is deduced from the behavioral models of individual components and their interconnection. –Represented by: Logic or schematic diagram Netlist (textual representation of schematic diagram) HDL description of circuit structures.

82. Chapter 282 Computer-aided Design (6) Structural models of a full-adder circuit: (a) schematic diagram, (b) netlist –In a netlist, each circuit element is defined as follows: gate_name, gate_type, output, input1, input2, …, inputN –VHDL structural model of a full-adder circuit: Figure 2.40.

83. Chapter 283 Computer-aided Design (7) Mixed-mode model –Contains both behavioral and structural components. –Mixed-mode model of the full-adder circuit: (a) full-adder block diagram, (b) circuit for sum function, (c) truth table for carry function.

84. Chapter 284 Computer-aided Design (8) Design synthesis process

85. Chapter 285 Computer-aided Design (9) Capture tools –Each circuit model in the design process must be captured in a format that can be stored and processed by a digital computer. –Schematic capture: an interactive graphics tool with which a designer draws a logic diagram.

86. Chapter 286 Computer-aided Design (10) Schematic capture process

87. Chapter 287 Computer-aided Design (11) Logic Simulation –Three primary purposes: 1. Logic verification: only logical correctness is checked. 2. Performance analysis: propagation delays and potential timing problems are analyzed. 3. Test development (fault simulation): helps develop optimal test set. –Simulation environment

88. Chapter 288 Computer-aided Design (12) Simulation Test Inputs –Test set: a carefully designed set of test inputs. –For logic verification, a list of input vectors is used (time is ignored). –For timing analysis, the time of each input change is also specified. functional test set for input tabular waveform full-adder waveform format format

89. Chapter 289 Computer-aided Design (13) Event-Driven Simulation –Event: a change in the value of a signal at a given time. –Event-driven simulation example for an AND gate:

90. Chapter 290 Computer-aided Design (14) Event-driven simulation procedure –Input test set is converted into a set of events. –The set of events are entered into an event queue (or event list). –In each simulation step, the first event is retrieved and is made to occur. –Output of each affected gate is recomputed, and new event is created. –Record of all events along with output results are maintained. –Simulation continues until the event queue is empty or time limit expires.

91. Chapter 291 Computer-aided Design (15) Debugging a full-adder using simulation erroneous simulation output: expanded simulation: full-adder error in s at time 3 isolates error to n3 circuit

92. Chapter 292 Computer-aided Design (16) Detection of static hazard via simulation –A glitch in g at time t 3 can be detected from the output waveforms. –This occurs because both e and f become 0 momentarily between t 2 and t 3.

93. Chapter 293 Computer-aided Design (17) Symbolic Logic Signal Values –Designers sometimes need signal values other than just 0 or 1. –Logic signal values are represented by a state and a strength. –A third state X represents an unknown state or a potential problem. –Truth tables for three-valued logic (with X added) –Signal strength values: Forcing (F): signal line is strongly forced to a given state. Resistive (R): signal line is weakly forced to a given state. Floating (Z): signal line is not forced forced at all. Unknown (U): signal strength cannot be determined.

94. Chapter 294 Computer-aided Design (18) Signal strengths are used to resolve conflicting gate outputs: output resolved in favor of output value stronger signal. unable to be resolved

95. Chapter 295 Computer-aided Design (19) Primitive Device Delay Models –Every primitive logic gate has an intrinsic delay. –A gate can be modeled as an ideal (zero-delay) gate and a transport delay element. –Different models of transport delays: Unit/Nominal Delay Rise Fall Delay Ambiguous or Min/Max Delay

96. Chapter 296 Computer-aided Design (20) Unit/Nominal Delay –Unit delay: assign to each gate in a circuit the same unit delay. –Nominal delay: delays are determined separately for each type of gate (e.g., on time unit for NOR and two time units for XOR).

97. Chapter 297 Computer-aided Design (21) Rise/Fall Delay –Different delays for 0 to 1 transition and 1 to 0 transition. –t PLH (rise time): propagation delay from low to high. –t PHL (fall time): propagation delay from high to low.

98. Chapter 298 Computer-aided Design (22) Ambiguous or Min/Max Delay –Sometimes it is impossible to predict exact rise or fall time of a signal. –For worst-case performance analysis, {t min, t max } is specified for each timing parameter.

99. Chapter 299 Computer-aided Design (23) A problem with min/max delay: the results tend to be pessimistic. circuit model worst-case delays: ambiguity region gets larger at each successive level

100. Chapter 2100 Computer-aided Design (24) Inertial Delay –An input value must persist for some minimum duration of time to provide the output with the needed inertia to change. –The minimum duration is called inertial delay. –Effect of inertial delay: –Gate model with both inertial delay and transport delay: