1. ELEN 468 Lecture 51 ELEN 468 Advanced Logic Design Lecture 5 User-Defined Primitives

2. ELEN 468 Lecture 52 Primitives Pre-defined primitives Total 26 pre-defined primitives All combinational Tri-state primitives have multiple output, others have single output User-Defined Primitives (UDP) Combinational or sequential Single output UDP vs. modules Used to model cell library Require less memory Simulate faster

3. ELEN 468 Lecture 53 UDP: Combinational Behavior primitive mux_prim ( out, select, a, b ); outputout; inputselect, a, b; table // selecta b: out 00 0: 0;// Each column -> a port 00 1: 0;// Last column -> single output 00 x: 0;// Input port column order = port list order 01 0: 1;// No inout port 01 1: 1;// Only 0, 1, x on input and output 01 x: 1;// A “z” input is treated as “x” 10 0: 0;// If an input vector is not in table, output -> “x” 11 0: 0; 1x 0: 0; 10 1: 1; 11 1: 1; 1x 1: 1; x0 0: 0;// Reduce pessimism x1 1: 1;// Without these 2 rows, output “x” for select = “x” endtable endprimitive mux_prim select out a b

4. ELEN 468 Lecture 54 Shorthand Notation primitive mux_prim ( out, select, a, b ); outputout; inputselect, a, b; table //selecta b: out 00 ?: 0;// ? => iteration of table entry over 0, 1, x. 01 ?: 1;// i.e., don’t care on the input 1? 0: 0; 1? 1: 1; ?0 0: 0; ?1 1: 1; endtable endprimitive mux_prim select out a b

5. ELEN 468 Lecture 55 UDP: Sequential Behavior In table description, n+2 columns for n input n input columns + internal state column + output (next state) column Output port -> reg variable

6. ELEN 468 Lecture 56 Level-sensitive Behavior primitive transparent_latch(out, enable, in); outputout; inputenable, in; regout; table //enableinstateout/next_state 11 :? :1; 10 :? :0; 0? :? :-;// ‘-’ -> no change x0 :0 :-; x1 :1 :-; endtable endprimitive Transparent latch enable inout

7. ELEN 468 Lecture 57 Edge-sensitive Behavior primitive d_flop( q, clock, d ); outputq; inputclock, d; regq; table // clockdstateq/next_state (01)0 :? :0;// Parentheses indicate signal transition (01)1 :? :1;// Rising clock edge (0?)1 :1 :1; (0?)0 :0 :0; (?0)? :? :-;// Falling clock edge ?(??) :? :-;// Steady clock endtable endprimitive clock dq d_flop

8. ELEN 468 Lecture 58 Mixed Behavior primitive jk_prim(q, clk, j, k, preset, clr); outputq; inputclk, j, k, preset, clr; regq; table //clkj kpre clr state q/next_state ?? ?0 1: ?: 1; ?? ?* 1: 1: 1;// ‘*’ -> (??) ?? ?1 0: ?: 0; ?? ?1 *: 0: 0; r0 01 1: ?: -;// ‘r’ -> (01) r0 11 1: ?: 0; r1 01 1: ?: 1; … b* ?? ?: ?: -;// b -> iterate through 0 and 1 … endtable endprimitive

9. ELEN 468 Lecture 59 Additional UDP Notations SymbolInterpretation ?Iteration of 0, 1, x bIteration of 0, 1 -No change (vw)Transition from v to w *All transition input (??) rTransition (01) fTransition (10) pIteration of (01), (0x), (x1) nIteration of (10), (x0), (1x)

10. ELEN 468 Lecture 510 Initialization of Sequential Primitives primitive d_flop( q, clock, data ); outputq; inputclock, data; regq; initialq = 0;// Set initial value of q table … endtable endprimitive

11. ELEN 468 Lecture 511 Exercises

12. ELEN 468 Lecture 512 True or False A Verilog reg variable can be the output of a pre-defined primitive, false A Verilog net variable cannot be assigned value by continuous assignment, false All module ports are scalars, false

13. ELEN 468 Lecture 513 Find Syntax Error reg [7:0] a, [15:0] b; reg [7:0] a; reg [15:0] b; integer [7:0] count_index; integer count_index[7:0];

14. ELEN 468 Lecture 514 Problems If a=0010, b=1010, c=0001, what is {a,b[3],b[1],c[2],c[0]} ? 00101101 A = 0101, B = 1001, what is A && B ? 0 A & (&B) ? 0101 & 0 = 0 In UDP notations, what is the difference between ‘r’ and ‘p’?