1. 1 Uttam Singisetti*, Man Hoi Wong, Jim Speck, and Umesh Mishra ECE and Materials Departments University of California, Santa Barbara, CA 2011 Device Research Conference Santa Barbara, CA, USA * uttam@ece.ucsb.edu Vertically scaled 5 nm GaN channel Enhancement-mode N-polar GaN MOS-HFET with 560 mS/mm g m and 0.76  -mm R on

2. 2 Outline Next generation GaN electronic devices N-polar GaN HEMTs Vertically scaled channel devices Results and Conclusion

3. 3 − GaN HEMTs: Power-switching, microwave, W-band power amplifiers − Future GaN devices for beyond mm-wave and to sub-mm-wave bands − Higher operating voltages than traditional III-Vs and Si  robust and rugged mixed signal ICs Next-generation mm-wave GaN devices John Albrecht, DARPA 1.3 W at 75 GHz Fujitsu, CSIC 2010 3 W at 87 GHz Caltech, HRL ISSSTT, 2011 W-band GaN power amplifiers

4. 4 − Aggressive dimensional scaling (L g and L sd ) − Vertical scaling with back-barrier and high-k dielectric − Parasitic resistances and capacitances scaling − Maintain high breakdown voltage Device goals and structure

5. 5 − No barrier to electron on top of 2-DEG  grading to narrowgap InN  low resistance contacts (0.027  -mm) 1 − AlGaN back  confinement of 2-DEG, control short channel effects 2 − Record high g m = 1105 mS/mm demonstrated 4 in D-mode − E-mode devices N-polar GaN Ultra-scaled N-polar HEMTs 1. S.Dasgupta, APL 2010, N-polar inverted HEMT No electron barrier 2. S. Rajan, IEEE TED 20113. NIdhi, DRC 2011

6. 6 Under gate Under S/D contacts* * S.Dasgupta, APL 2010 Under sidewall AlN removed under sidewall E-mode device structure and design Top AlN depletes 2-DEG under gate Under gate

7. 7 Short channel effect and vertical scaling V th roll off with gate length Vertical scaling needed to maintain E-mode at sub-50 nm gate lengths Vertical scaling for high R ds at sub-50-nm gate lengths V t roll-off with gate length 20 nm GaN channel 1 8 nm GaN channel 2 Poor saturation at sub-100nm L g 1. U.Singisetti, EDL 2010,2. U.Singisetti, APEX 2011 Need 5 nm GaN channel for sub-50 nm devices

8. 8 Ultra-thin channel challenges: Mobility Need 5 nm thick GaN channel for sub-50 nm devices Mobility drops with decreasing GaN channel thickness Interface roughness, surface roughness scattering increases* * U.Singisetti, ISCS 2011 QW thickness flutuations GaN

9. 9 Mobility dependence on Si doping Low mobility in high-3D Si density samples High Si density may lead to rougher interface Si : 5 e18 cm -3 Si : 2 e 19 cm -3

10. 10 Ultra-thin channel challenges: surface depletion Surface depletion increases in thin channels Lower charge in the access regions lead to higher source resistance

11. 11 5nm-GaN channel device design Graded back-barrier high mobility and t reduce the effect of trap* 4.5 nm of Al 2 O 3 gate dielectric 1.6×10 13 cm -2 in the sidewall access regions after top-AlN etch * M -H Wong, DRC 2011.

12. 12 Device fabrication process* * U.Singisetti, EDL 2010.

13. 13 DC characteristics Reduced short channel effects due to vertical scaling and graded barrier 1 Peak g m = 560 mS/mm, peak I d = 1.3 A/mm Positive threshold voltage of 1.3 V * M -H Wong, DRC 2011.

14. 14 DC characteristics: R on and R s Record low R on = 0.61  -mm* for L g = 115 nm InN growth optimization for complete coverage near the gate Regrowth sheet resistance = 100  /sq,  c = 5  -mm Gate InN Gate No InN InN

15. 15 RF performance: peak f t peak f t = 115 GHz at V ds = 4.5 V and V gs = 2.5 V low f max = 30 GHz due to thin W gate ( ~ 1500  /sq)

16. 16 RF performance : small-signal model Equivalent circuit model S 21 /5 S 22 S 12 *3 S 11 Measured (circles) Modeled (line)

17. 17 V gs corrosponding to peak f t is 2.5 V Absence of drain delay RF performance: bias dependence

18. 18 Conclusions and future work Demonstrated vertically scaled 5-nm GaN channel MOS-HFET devices E-mode with V th = 1.3 V, peak g m = 560 mS/mm, peak I d = 1.3 A/mm Record low R on = 0.61  -mm, for 115 nm E-mode GaN HEMTs peak f t = 115 GHz for 120 nm gate length device This work was supported by DARPA NEXT program Future work Scale the gate length to 50 nm Top gate for f max Scale the gate dielectric (HfO 2, ZrO 2 )

19. 19 New measurements post DRC peak f t = 122 GHz at V ds = 5.5 V and V gs = 2.5 V f t -L g product of 14 GHz-  m

20. 20 New measurements post DRC maximum I on /I off ratio ~ 2×10 5 Breakdown voltage 8. 6 V dielectric breakdown