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Parallel compressing system for satellite on programmable chip Yifat Manzor Yifat Manzor & Reshef Dahan Supervisor: Eran Segev Part B.

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Presentation on theme: "Parallel compressing system for satellite on programmable chip Yifat Manzor Yifat Manzor & Reshef Dahan Supervisor: Eran Segev Part B."— Presentation transcript:

1 Parallel compressing system for satellite on programmable chip Yifat Manzor Yifat Manzor & Reshef Dahan Supervisor: Eran Segev Part B

2 Satellite image Input Data rate from one sensor line   B/W Picture   Range – 2.5 km width   Velocity - 8 km/sec   4 Pixels per 1m ² Rate = 80 Mpix/sec Streaming Data 12-bit per pixel 5,000 pix 16,000 lines/sec 80 Mpixel image

3 System demands: » 80Mpix/sec input data rate. » Image width – 5000 pixel ADV202 Single compressing chip capabilities: » 27 Mpix/sec maximum input data rate » 25 MByte/sec maximum output rate » Maximum image width – 4096 pixel » Maximum image length – infinity

4 Solution MAIN IDEA To generate parallel processing by separating the picture to 3 compressors 1667pix 1666pix 3 16,000 lines/sec Tile

5 Memory ADV202 Data in System Description camera XILINX Virtex2Pro ADV202 model Checksum Generator Data Generator RESET LED Compressor Controller System

6 CONTROLLER

7 CONTROLLER block diagram Compressed data Input Data DIVIDER Compression Unit MERGER

8 Divider DIVIDER Compression Unit MERGER Compression Unit

9 Divider Simulation Results Divider Simulation Results

10 compression unit DIVIDER Compression Unit MERGER

11 25MHz Compression unit - Architecture 27MHz funnel adv_202 model comp_data buff Interrupt_generator From divider 80MHz 8 bits12 bits To/from merger To merger 80MHz

12 Compression unit Simulation Results

13 merger DIVIDER Compression Unit MERGER compressed data package header Output Output :

14 Merger - Architecture header generator calculator 80MHz To/from unit 0 To/from unit 2 To/from unit 1 Compressed output 25MHz

15 Merger – Architecture cont. calculator Interrupt from unit 0 output generator queue generator queue To\from header generator Data to/from unit 0 Data to/from unit 1 Data to/from unit 2 80MHz Interrupt from unit 2 Interrupt from unit 1 25MHz Compressed output

16 Merger Simulation Results

17 Controller Simulation Results

18 Testing Environment DIVIDERMERGER Comp. Unit Comp. Unit Comp. Unit Virtex2Pro Generator Check Results Memory Data in System

19 DIVIDERMERGER Comp. Unit Comp. Unit Comp. Unit Controller Data Generator Checksum Generator RESETLED Virtex2Pro DCM Testing Environment System

20 Simulation Results

21 Summary

22 Summary Cont.


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