1. CS151B Computer Systems Architecture Winter 2002 TuTh 2-4pm - 2444 BH Instructor: Prof. Jason Cong Lecture 6 – ALU Design II: Multiply, Divide, and Floating Point Operations

2. 2 CS151BJason Cong Review: ALU Design °Bit-slice plus extra on the two ends °Overflow means number too large for the representation °Carry-look ahead and other adder tricks A M S 32 4 Ovflw ALU0 a0b0 cinco s0 ALU31 a31b31 cinco s31 B32 C/L to produce select, comp, c-in signed-arith and cin xor co

3. 3 CS151BJason Cong Review: Elements of the Design Process °Divide and Conquer (e.g., ALU) Formulate a solution in terms of simpler components. Design each of the components (subproblems) °Generate and Test (e.g., ALU) Given a collection of building blocks, look for ways of putting them together that meets requirement °Successive Refinement (e.g., multiplier, divider) Solve "most" of the problem (i.e., ignore some constraints or special cases), examine and correct shortcomings. °Formulate High-Level Alternatives (e.g., shifter) Articulate many strategies to "keep in mind" while pursuing any one approach. °Work on the Things you Know How to Do The unknown will become “obvious” as you make progress.

4. 4 CS151BJason Cong Review: Summary of the Design Process Hierarchical Design to manage complexity Top Down vs. Bottom Up vs. Successive Refinement Importance of Design Representations: Block Diagrams Decomposition into Bit Slices Truth Tables, K-Maps Circuit Diagrams Other Descriptions: state diagrams, timing diagrams, reg xfer,... Optimization Criteria: Gate Count [Package Count] Logic Levels Fan-in/Fan-out Power top down bottom up Area Delay CostDesign timePin Out

5. 5 CS151BJason Cong MIPS arithmetic instructions °InstructionExampleMeaningComments °add add $1,$2,$3$1 = $2 + $33 operands; exception possible °subtractsub $1,$2,$3$1 = $2 – $33 operands; exception possible °add immediateaddi $1,$2,100$1 = $2 + 100+ constant; exception possible °add unsignedaddu $1,$2,$3$1 = $2 + $33 operands; no exceptions °subtract unsignedsubu $1,$2,$3$1 = $2 – $33 operands; no exceptions °add imm. unsign.addiu $1,$2,100$1 = $2 + 100+ constant; no exceptions °multiply mult $2,$3Hi, Lo = $2 x $364-bit signed product °multiply unsignedmultu$2,$3Hi, Lo = $2 x $3 64-bit unsigned product °divide div $2,$3Lo = $2 ÷ $3,Lo = quotient, Hi = remainder ° Hi = $2 mod $3 °divide unsigned divu $2,$3Lo = $2 ÷ $3,Unsigned quotient & remainder ° Hi = $2 mod $3 °Move from Himfhi $1$1 = HiUsed to get copy of Hi °Move from Lomflo $1$1 = LoUsed to get copy of Lo

6. 6 CS151BJason Cong MULTIPLY (unsigned) °Paper and pencil example (unsigned): Multiplicand 1000 Multiplier 1001 1000 0000 0000 1000 Product 01001000 °m bits x n bits = m+n bit product °Binary makes it easy: 0 => place 0 ( 0 x multiplicand) 1 => place a copy ( 1 x multiplicand) °4 versions of multiply hardware & algorithm: successive refinement

7. 7 CS151BJason Cong Unsigned Combinational Multiplier °Stage i accumulates A * 2 i if B i == 1 °Q: How much hardware for 32 bit multiplier? Critical path? B0B0 A0A0 A1A1 A2A2 A3A3 A0A0 A1A1 A2A2 A3A3 A0A0 A1A1 A2A2 A3A3 A0A0 A1A1 A2A2 A3A3 B1B1 B2B2 B3B3 P0P0 P1P1 P2P2 P3P3 P4P4 P5P5 P6P6 P7P7 0000

8. 8 CS151BJason Cong How does it work? °at each stage shift A left ( x 2) °use next bit of B to determine whether to add in shifted multiplicand °accumulate 2n bit partial product at each stage B0B0 A0A0 A1A1 A2A2 A3A3 A0A0 A1A1 A2A2 A3A3 A0A0 A1A1 A2A2 A3A3 A0A0 A1A1 A2A2 A3A3 B1B1 B2B2 B3B3 P0P0 P1P1 P2P2 P3P3 P4P4 P5P5 P6P6 P7P7 0000 000

9. 9 CS151BJason Cong Unisigned shift-add multiplier (version 1) °64-bit Multiplicand reg, 64-bit ALU, 64-bit Product reg, 32-bit multiplier reg Product Multiplier Multiplicand 64-bit ALU Shift Left Shift Right Write Control 32 bits 64 bits Multiplier = datapath + control

10. 10 CS151BJason Cong Multiply Algorithm Version 1 °ProductMultiplierMultiplicand 0000 0000 00110000 0010 °0000 001000010000 0100 °0000 011000000000 1000 °0000 0110 3. Shift the Multiplier register right 1 bit. Done Yes: 32 repetitions 2. Shift the Multiplicand register left 1 bit. No: < 32 repetitions 1. Test Multiplier0 Multiplier0 = 0 Multiplier0 = 1 1a. Add multiplicand to product & place the result in Product register 32nd repetition? Start

11. 11 CS151BJason Cong Observations on Multiply Version 1 °1 clock per cycle =>  100 clocks per multiply Ratio of multiply to add 5:1 to 100:1 °1/2 bits in multiplicand always 0 => 64-bit adder is wasted °0’s inserted in left of multiplicand as shifted => least significant bits of product never changed once formed °Instead of shifting multiplicand to left, shift product to right?

12. 12 CS151BJason Cong MULTIPLY HARDWARE Version 2 °32-bit Multiplicand reg, 32 -bit ALU, 64-bit Product reg, 32-bit Multiplier reg Product Multiplier Multiplicand 32-bit ALU Shift Right Write Control 32 bits 64 bits Shift Right

13. 13 CS151BJason Cong How to think of this? B0B0 A0A0 A1A1 A2A2 A3A3 A0A0 A1A1 A2A2 A3A3 A0A0 A1A1 A2A2 A3A3 A0A0 A1A1 A2A2 A3A3 B1B1 B2B2 B3B3 P0P0 P1P1 P2P2 P3P3 P4P4 P5P5 P6P6 P7P7 0000 Remember original combinational multiplier:

14. 14 CS151BJason Cong Simply warp to let product move right... °Multiplicand stay’s still and product moves right B0B0 B1B1 B2B2 B3B3 P0P0 P1P1 P2P2 P3P3 P4P4 P5P5 P6P6 P7P7 0000 A0A0 A1A1 A2A2 A3A3 A0A0 A1A1 A2A2 A3A3 A0A0 A1A1 A2A2 A3A3 A0A0 A1A1 A2A2 A3A3

15. 15 CS151BJason Cong Multiply Algorithm Version 2 3. Shift the Multiplier register right 1 bit. Done Yes: 32 repetitions 2. Shift the Product register right 1 bit. No: < 32 repetitions 1. Test Multiplier0 Multiplier0 = 0 Multiplier0 = 1 1a. Add multiplicand to the left half of product & place the result in the left half of Product register 32nd repetition? Start 0000 0000 0011 0010 1: 0010 0000 0011 0010 2: 0001 0000 0011 0010 3: 0001 0000 0001 0010 1: 0011 0000 0001 0010 2: 0001 1000 0001 0010 3: 0001 1000 0000 0010 1: 0001 1000 0000 0010 2: 0000 1100 0000 0010 3: 0000 1100 0000 0010 1: 0000 1100 0000 0010 2: 0000 0110 0000 0010 3: 0000 0110 0000 0010 0000 0110 0000 0010 Product Multiplier Multiplicand

16. 16 CS151BJason Cong Still more wasted space! 3. Shift the Multiplier register right 1 bit. Done Yes: 32 repetitions 2. Shift the Product register right 1 bit. No: < 32 repetitions 1. Test Multiplier0 Multiplier0 = 0 Multiplier0 = 1 1a. Add multiplicand to the left half of product & place the result in the left half of Product register 32nd repetition? Start 0000 0000 0011 0010 1: 0010 0000 0011 0010 2: 0001 0000 0011 0010 3: 0001 0000 0001 0010 1: 0011 0000 0001 0010 2: 0001 1000 0001 0010 3: 0001 1000 0000 0010 1: 0001 1000 0000 0010 2: 0000 1100 0000 0010 3: 0000 1100 0000 0010 1: 0000 1100 0000 0010 2: 0000 0110 0000 0010 3: 0000 0110 0000 0010 0000 0110 0000 0010 Product Multiplier Multiplicand

17. 17 CS151BJason Cong Observations on Multiply Version 2 °Product register wastes space that exactly matches size of multiplier => combine Multiplier register and Product register

18. 18 CS151BJason Cong MULTIPLY HARDWARE Version 3 °32-bit Multiplicand reg, 32 -bit ALU, 64-bit Product reg, (0-bit Multiplier reg) Product (Multiplier) Multiplicand 32-bit ALU Write Control 32 bits 64 bits Shift Right

19. 19 CS151BJason Cong Multiply Algorithm Version 3 MultiplicandProduct 00100000 0011 Done Yes: 32 repetitions 2. Shift the Product register right 1 bit. No: < 32 repetitions 1. Test Product0 Product0 = 0 Product0 = 1 1a. Add multiplicand to the left half of product & place the result in the left half of Product register 32nd repetition? Start

20. 20 CS151BJason Cong Observations on Multiply Version 3 °2 steps per bit because Multiplier & Product combined °MIPS registers Hi and Lo are left and right half of Product °Gives us MIPS instruction MultU °How can you make it faster? °What about signed multiplication? easiest solution is to make both positive & remember whether to complement product when done (leave out the sign bit, run for 31 steps) apply definition of 2’s complement -need to sign-extend partial products and subtract at the end Booth’s Algorithm is elegant way to multiply signed numbers using same hardware as before and save cycles -can handle multiple bits at a time

21. 21 CS151BJason Cong Motivation for Booth’s Algorithm °Example 2 x 6 = 0010 x 0110: 0010 x 0110 + 0000shift (0 in multiplier) + 0010 add (1 in multiplier) + 0010 add (1 in multiplier) + 0000 shift (0 in multiplier) 00001100 °ALU with add or subtract gets same result in more than one way: 6= – 2 + 8 0110 = – 00010 + 01000 = 11110 + 01000 °For example ° 0010 x 0110 0000 shift (0 in multiplier) – 0010 sub (first 1 in multpl.). 0000 shift (mid string of 1s). +0010 add (prior step had last 1) 00001100

22. 22 CS151BJason Cong Booth’s Algorithm Current BitBit to the RightExplanationExampleOp 10Begins run of 1s0001111000sub 11Middle of run of 1s0001111000none 01End of run of 1s0001111000add 00Middle of run of 0s0001111000none Originally for Speed (when shift was faster than add) °Replace a string of 1s in multiplier with an initial subtract when we first see a one and then later add for the bit after the last one 0 1 1 1 1 0 beginning of runend of run middle of run –1 + 10000 01111

23. 23 CS151BJason Cong Booths Example (2 x 7) 1a. P = P - m1110 +1110 1110 0111 0shift P (sign ext) 1b. 00101111 0011 111 -> nop, shift 2.00101111 1001 111 -> nop, shift 3.00101111 1100 101 -> add 4a.0010 +0010 0001 1100 1shift 4b.00100000 1110 0done OperationMultiplicandProductnext? 0. initial value00100000 0111 010 -> sub

24. 24 CS151BJason Cong Booths Example (2 x -3) 1a. P = P - m1110 +1110 1110 1101 0shift P (sign ext) 1b. 00101111 0110 101 -> add + 0010 2a.0001 0110 1shift P 2b.00100000 1011 010 -> sub +1110 3a.00101110 1011 0shift 3b.0010 1111 0101 111 -> nop 4a1111 0101 1 shift 4b.00101111 1010 1 done OperationMultiplicandProductnext? 0. initial value00100000 1101 010 -> sub

25. 25 CS151BJason Cong MIPS logical instructions °InstructionExampleMeaningComment °and and $1,$2,$3$1 = $2 & $33 reg. operands; Logical AND °or or $1,$2,$3$1 = $2 | $33 reg. operands; Logical OR °xor xor $1,$2,$3$1 = $2  $33 reg. operands; Logical XOR °nor nor $1,$2,$3$1 = ~($2 |$3)3 reg. operands; Logical NOR °and immediate andi $1,$2,10$1 = $2 & 10Logical AND reg, constant °or immediate ori $1,$2,10$1 = $2 | 10Logical OR reg, constant °xor immediate xori $1, $2,10 $1 = ~$2 &~10Logical XOR reg, constant °shift left logical sll $1,$2,10$1 = $2 << 10Shift left by constant °shift right logical srl $1,$2,10$1 = $2 >> 10Shift right by constant °shift right arithm. sra $1,$2,10$1 = $2 >> 10Shift right (sign extend) °shift left logical sllv $1,$2,$3$1 = $2 << $3 Shift left by variable °shift right logical srlv $1,$2, $3 $1 = $2 >> $3 Shift right by variable °shift right arithm. srav $1,$2, $3 $1 = $2 >> $3 Shift right arith. by variable

26. 26 CS151BJason Cong Shifters Two kinds: logical-- value shifted in is always "0" arithmetic-- on right shifts, sign extend msblsb"0" msblsb"0" Note: these are single bit shifts. A given instruction might request 0 to 32 bits to be shifted!

27. 27 CS151BJason Cong Combinational Shifter from MUXes °What comes in the MSBs? °How many levels for 32-bit shifter? 1 0 sel A B D Basic Building Block 8-bit right shifter 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 S 2 S 1 S 0 A0A0 A1A1 A2A2 A3A3 A4A4 A5A5 A6A6 A7A7 R0R0 R1R1 R2R2 R3R3 R4R4 R5R5 R6R6 R7R7

28. 28 CS151BJason Cong Barrel Shifter Technology-dependent solutions: transistor per switch

29. 29 CS151BJason Cong Barrel Shifter (2) °2N-1 inputs (diagonal) °N outputs (horizontal) °N control signals (vertical) – only one can be true °Example – 2-bit right logical shift SR2=1 A0-A3: inputs A4 = A5 = 1

30. 30 CS151BJason Cong Divide: Paper & Pencil 1001 Quotient Divisor 1000 1001010 Dividend –1000 10 101 1010 –1000 10 Remainder (or Modulo result) See how big a number can be subtracted, creating quotient bit on each step Binary => 1 * divisor or 0 * divisor Dividend = Quotient x Divisor + Remainder => | Dividend | = | Quotient | + | Divisor | 3 versions of divide, successive refinement

31. 31 CS151BJason Cong DIVIDE HARDWARE Version 1 °64-bit Divisor reg, 64-bit ALU, 64-bit Remainder reg, 32-bit Quotient reg Remainder Quotient Divisor 64-bit ALU Shift Right Shift Left Write Control 32 bits 64 bits

32. 32 CS151BJason Cong 2b. Restore the original value by adding the Divisor register to the Remainder register, & place the sum in the Remainder register. Also shift the Quotient register to the left, setting the new least significant bit to 0. Divide Algorithm Version 1 °Takes n+1 steps for n-bit Quotient & Rem. Remainder QuotientDivisor 0000 0111 00000010 0000 Test Remainder Remainder < 0 Remainder  0 1. Subtract the Divisor register from the Remainder register, and place the result in the Remainder register. 2a. Shift the Quotient register to the left setting the new rightmost bit to 1. 3. Shift the Divisor register right1 bit. Done Yes: n+1 repetitions (n = 4 here) Start: Place Dividend in Remainder n+1 repetition? No: < n+1 repetitions

33. 33 CS151BJason Cong Divide Algorithm I example (7 / 2) Remainder QuotientDivisor 0000 0111000000010 0000 1:1110 0111000000010 0000 2:0000 0111000000010 0000 3:0000 0111000000001 0000 1:1111 0111000000001 0000 2:0000 0111000000001 0000 3:0000 0111000000000 1000 1:1111 1111000000000 1000 2:0000 0111000000000 1000 3:0000 0111000000000 0100 1:0000 0011000000000 0100 2:0000 0011000010000 0100 3:0000 0011000010000 0010 1:0000 0001000010000 0010 2:0000 0001000110000 0010 3:0000 0001000110000 0010 Answer: Quotient = 3 Remainder = 1

34. 34 CS151BJason Cong Observations on Divide Version 1 °1/2 bits in divisor always 0 => 1/2 of 64-bit adder is wasted => 1/2 of divisor is wasted °Instead of shifting divisor to right, shift remainder to left? °1st step cannot produce a 1 in quotient bit (otherwise too big) => switch order to shift first and then subtract, can save 1 iteration

35. 35 CS151BJason Cong Divide Algorithm I example: wasted space Remainder QuotientDivisor 0000 0111000000010 0000 1:1110 0111000000010 0000 2:0000 0111000000010 0000 3:0000 0111000000001 0000 1:1111 0111000000001 0000 2:0000 0111000000001 0000 3:0000 0111000000000 1000 1:1111 1111000000000 1000 2:0000 0111000000000 1000 3:0000 0111000000000 0100 1:0000 0011000000000 0100 2:0000 0011000010000 0100 3:0000 0011000010000 0010 1:0000 0001000010000 0010 2:0000 0001000110000 0010 3:0000 0001000110000 0010

36. 36 CS151BJason Cong Divide: Paper & Pencil 01010 Quotient Divisor 0001 00001010 Dividend 00001 –0001 0000 0001 –0001 0 00 Remainder (or Modulo result) Notice that there is no way to get a 1 in leading digit! (this would be an overflow, since quotient would have n+1 bits)

37. 37 CS151BJason Cong DIVIDE HARDWARE Version 2 °32-bit Divisor reg, 32-bit ALU, 64-bit Remainder reg, 32-bit Quotient reg Remainder Quotient Divisor 32-bit ALU Shift Left Write Control 32 bits 64 bits Shift Left

38. 38 CS151BJason Cong Divide Algorithm Version 2 Remainder Quotient Divisor 0000 0111 0000 0010 3b. Restore the original value by adding the Divisor register to the left half of the Remainderregister, &place the sum in the left half of the Remainder register. Also shift the Quotient register to the left, setting the new least significant bit to 0. Test Remainder Remainder < 0 Remainder  0 2. Subtract the Divisor register from the left half of the Remainder register, & place the result in the left half of the Remainder register. 3a. Shift the Quotient register to the left setting the new rightmost bit to 1. 1. Shift the Remainder register left 1 bit. Done Yes: n repetitions (n = 4 here) nth repetition? No: < n repetitions Start: Place Dividend in Remainder

39. 39 CS151BJason Cong Observations on Divide Version 2 °Eliminate Quotient register by combining with Remainder as shifted left Start by shifting the Remainder left as before. Thereafter loop contains only two steps because the shifting of the Remainder register shifts both the remainder in the left half and the quotient in the right half The consequence of combining the two registers together and the new order of the operations in the loop is that the remainder will shifted left one time too many. Thus the final correction step must shift back only the remainder in the left half of the register

40. 40 CS151BJason Cong DIVIDE HARDWARE Version 3 °32-bit Divisor reg, 32 -bit ALU, 64-bit Remainder reg, (0-bit Quotient reg) Remainder (Quotient) Divisor 32-bit ALU Write Control 32 bits 64 bits Shift Left “HI”“LO”

41. 41 CS151BJason Cong Divide Algorithm Version 3 Remainder Divisor 0000 01110010 3b. Restore the original value by adding the Divisor register to the left half of the Remainderregister, &place the sum in the left half of the Remainder register. Also shift the Remainder register to the left, setting the new least significant bit to 0. Test Remainder Remainder < 0 Remainder  0 2. Subtract the Divisor register from the left half of the Remainder register, & place the result in the left half of the Remainder register. 3a. Shift the Remainder register to the left setting the new rightmost bit to 1. 1. Shift the Remainder register left 1 bit. Done. Shift left half of Remainder right 1 bit. Yes: n repetitions (n = 4 here) nth repetition? No: < n repetitions Start: Place Dividend in Remainder

42. 42 CS151BJason Cong Observations on Divide Version 3 °Same Hardware as Multiply: just need ALU to add or subtract, and 64-bit register to shift left or shift right °Hi and Lo registers in MIPS combine to act as 64-bit register for multiply and divide °Signed Divides: Simplest is to remember signs, make positive, and complement quotient and remainder if necessary Note: Dividend and Remainder must have same sign Note: Quotient negated if Divisor sign & Dividend sign disagree e.g., –7 ÷ 2 = –3, remainder = –1 What about? –7 ÷ 2 = –4, remainder = +1 °Possible for quotient to be too large: if divide 64-bit integer by 1, quotient is 64 bits (“called saturation”)

43. 43 CS151BJason Cong What is in a number? °What can be represented in N bits? °Unsigned0to2 N - 1 °2s Complement- 2 N-1 to2 N-1 - 1 °1s Complement-2 N-1 +1to2 N-1 -1 °Excess M 2 -M to2 N - M - 1 (E = e + M) ° BCD0to10 N/4 - 1 °But, what about? very large numbers?9,349,398,989,787,762,244,859,087,678 very small number?0.0000000000000000000000045691 rationals 2/3 irrationals transcendentalse, 

44. 44 CS151BJason Cong Recall Scientific Notation 6.02 x 10 1.673 x 10 23 -24 exponent radix (base) Mantissa decimal point Sign, magnitude IEEE F.P. ± 1.M x 2 e - 127 °Issues: Arithmetic (+, -, *, / ) Representation, Normal form Range and Precision Rounding Exceptions (e.g., divide by zero, overflow, underflow) Errors Properties ( negation, inversion, if A  B then A - B  0 )

45. 45 CS151BJason Cong Review from Prerequisties: Floating-Point Arithmetic Representation of floating point numbers in IEEE 754 standard: single precision 1823 sign exponent: excess 127 binary integer mantissa: sign + magnitude, normalized binary significand w/ hidden integer bit: 1.M actual exponent is e = E - 127 SE M N = (-1) 2 (1.M) S E-127 0 < E < 255 0 = 0 00000000 0... 0 -1.5 = 1 01111111 10... 0 Magnitude of numbers that can be represented is in the range: 2 -126 (1.0) to2 127 (2 - 2 -23 ) which is approximately: 1.8 x 10 -38 to3.40 x 10 38 (integer comparison valid on IEEE Fl.Pt. numbers of same sign!)

46. 46 CS151BJason Cong Basic Addition Algorithm/Multiply issues For addition (or subtraction) this translates into the following steps: (1) compute Ye - Xe (getting ready to align binary point) (2) right shift Xm that many positions to form Xm 2 (3) compute Xm 2 + Ym if representation demands normalization, then normalization step follows: (4) left shift result, decrement result exponent (e.g., 0.001xx…) right shift result, increment result exponent (e.g., 101.1xx…) continue until MSB of data is 1 (NOTE: Hidden bit in IEEE Standard) (5) for multiply, doubly biased exponent must be corrected: Xe = 7 Ye = -3 Excess 8 extra subtraction step of the bias amount (6) if result is 0 mantissa, may need to zero exponent by special step Xe-Ye Xe = 1111 Ye = 0101 10100 = 15 = 5 20 = 7 + 8 = -3 + 8 4 + 8 + 8

47. 47 CS151BJason Cong Extra Bits for Rounding "Floating Point numbers are like piles of sand; every time you move one you lose a little sand, but you pick up a little dirt." How many extra bits? IEEE: As if computed the result exactly and rounded. Need of extra bits: For addition: 1.xxxxx1.xxxxx1.xxxxx +1.xxxxx0.001xxxxx0.01xxxxx 1x.xxxxy 1.xxxxxyyy 1x.xxxxyyy Needed: post-normalization pre-normalization pre and post °Guard Digits: digits to the right of the first p digits of significand to guard against loss of digits – can later be shifted left into first P places during normalization. °IEEE 754 keeps 2 extra bits: guard bit and round bit

48. 48 CS151BJason Cong Rouding with Guard Digits Example: 2.56x10 0 + 2.34x10 2 (assuming 3 significant digits) With guard digits Without guard digits 2.34002.34 + 0.0256 + 0.02 -------------------- ------------- 2.36562.36 Rounded to 2.37 one round digit must be carried to the right of the guard digit so that after a normalizing left shift, the result can be rounded, according to the value of the round digit ulp: units in the last place IEEE 754 guarantees the accuracy within one-half ulp

49. 49 CS151BJason Cong Sticky Bit Additional bit to the right of the round digit to better fine tune rounding d0. d1 d2 d3... dp-1 0 0 0 0. 0 0 X... X X X S X X S + Sticky bit: set to 1 if exist any 1 bit fall off the end of the round digit Allow machine to see difference between 0.50…00 vs 0.50…01 May set during addition when shifting the smaller number to the right

50. 50 CS151BJason Cong Rounding Methods IEEE Standard: four rounding modes: round to nearest even (default) round towards plus infinity round towards minus infinity round towards 0 round to nearest even: round digit < B/2 then truncate > B/2 then round up (add 1 to ULP: unit in last place) = B/2 then round to nearest even digit (LSB=1, add 1, otherwise, truncate => LSB is 0 after rounding) it can be shown that this strategy minimizes the mean error introduced by rounding

51. 51 CS151BJason Cong Denormalized (Subnormal) Numbers 02 2 2 -bias 1-bias 2-bias Suppose B = 2, 3-bit mantissa denorm gap The gap between 0 and the next representable number is much larger than the gaps between nearby representable numbers. IEEE standard uses denormalized numbers (exp. =0; significand <>0) to fill in the gap, making the distances between numbers near 0 more alike. 02 2 2 -bias 1-bias 2-bias p bits of precision p-1 bits of precision same spacing, half as many values! NOTE: PDP-11, VAX cannot represent subnormal numbers. These machines underflow to zero instead.

52. 52 CS151BJason Cong Infinity and NaNs result of operation overflows, i.e., is larger than the largest number that can be represented overflow is not the same as divide by zero (raises a different exception) +/- infinity S 1... 1 0... 0 It may make sense to do further computations with infinity e.g., X/0 > Y may be a valid comparison Not a number, but not infinity (e.q. sqrt(-4)) invalid operation exception (unless operation is = or =) NaN S 1... 1 non-zero NaNs propagate: f(NaN) = NaN HW decides what goes here

53. 53 CS151BJason Cong Pentium Bug °Some don’t-care entry was introduced incorrectly in a lookup-table for floating-point division °First 11 bits to right of decimal point always correct: bits 12 to 52 where bug can occur (4th to 15th decimal digits) °FP divisors near integers 3, 9, 15, 21, 27 are dangerous ones: 3.0 > d  3.0 - 36 x 2 –22, 9.0 > d  9.0 - 36 x 2 –20 15.0 > d  15.0 - 36 x 2 –20, 21.0 > d  21.0 - 36 x 2 –19 °0.333333 x 9 could be problem °In Microsoft Excel, try (4,195,835 / 3,145,727) * 3,145,727 = 4,195,835 => not a Pentium with bug = 4,195,579 => Pentium with bug (assuming Excel doesn’t already have SW bug patch) Rarely noticed since error in 5th significant digit Success of IEEE standard made discovery possible: ­ all computers should get same answer

54. 54 CS151BJason Cong Pentium Bug Time line °June 1994: Intel discovers bug in Pentium: takes months to make change, reverify, put into production: plans good chips in January 1995 4 to 5 million Pentiums produced with bug °Scientist suspects errors and posts on Internet in September 1994 °Nov. 22 Intel Press release: “Can make errors in 9th digit... Most engineers and financial analysts need only 4 of 5 digits. Theoretical mathematician should be concerned.... So far only heard from one.” °Intel claims happens once in 27,000 years for typical spread sheet user: 1000 divides/day x error rate assuming numbers random °Dec 12: IBM claims happens once per 24 days: Bans Pentium sales 5000 divides/second x 15 minutes = 4,200,000 divides/day IBM statement: http://www.ibm.com/Features/pentium.html Intel said it regards IBM's decision to halt shipments of its Pentium processor-based systems as unwarranted.

55. 55 CS151BJason Cong Pentium conclusion: Dec. 21, 1994 $500M write-off “To owners of Pentium processor-based computers and the PC community: We at Intel wish to sincerely apologize for our handling of the recently publicized Pentium processor flaw. The Intel Inside symbol means that your computer has a microprocessor second to none in quality and performance. Thousands of Intel employees work very hard to ensure that this is true. But no microprocessor is ever perfect. What Intel continues to believe is technically an extremely minor problem has taken on a life of its own. Although Intel firmly stands behind the quality of the current version of the Pentium processor, we recognize that many users have concerns. We want to resolve these concerns. Intel will exchange the current version of the Pentium processor for an updated version, in which this floating-point divide flaw is corrected, for any owner who requests it, free of charge anytime during the life of their computer. Just call 1-800-628-8686.” Sincerely, Andrew S. Grove Craig R. Barrett Gordon E. Moore President /CEO Executive Vice President Chairman of the Board &COO

56. 56 CS151BJason Cong Summary °Multiply: successive refinement to see final design 32-bit Adder, 64-bit shift register, 32-bit Multiplicand Register Booth’s algorithm to handle signed multiplies There are algorithms that calculate many bits of multiply per cycle (see exercises 4.36 to 4.39 in COD) °Shifter: success refinement 1/bit at a time shift register to barrel shifter °Divide can use same hardware as multiply: Hi & Lo registers in MIPS °Bits have no inherent meaning: operations determine whether they are really ASCII characters, integers, floating point numbers °Floating point basically follows paper and pencil method of scientific notation using integer algorithms for multiply and divide of significands °IEEE 754 requires good rounding; special values for NaN, Infinity

57. 57 CS151BJason Cong To Get More Information °Chapter 4 of your text book: David Patterson & John Hennessy, “Computer Organization & Design,” Morgan Kaufmann Publishers, 1994. °David Winkel & Franklin Prosser, “The Art of Digital Design: An Introduction to Top-Down Design,” Prentice-Hall, Inc., 1980. °Kai Hwang, “Computer Arithmetic: Principles, architecture, and design”, Wiley 1979

58. 58 CS151BJason Cong Acknowledgements °The majority of slides in this lecture are from UC Berkeley for their CS152 course (David Patterson, John Kubiatowicz, …)