1. 11/29/2007ELEC 6270-001 Class Project Presentation1 LOW VOLTAGE OPERATION OF A 32-BIT ADDER USING LEVEL CONVERTERS Mohammed Ashfaq Shukoor ECE Department Auburn University

2. 11/29/2007 ELEC 6270-001 Low-Power Design of Electronic Circuits 2 Objectives  To reduce the power consumption by operating the adder at reduced voltage, coupled with level converters.  To study the effect of Voltage reduction on the Power consumption and delay of the adder  To characterize the Level Converters for power consumption and delay

3. 11/29/2007 ELEC 6270-001 Low-Power Design of Electronic Circuits 3 Setup for Low Voltage Operation 32-bit Adder High Voltage inputs Low-to-High Level Converter VDD_L 65 33 High Voltage Outputs Low Voltage outputs

4. 11/29/2007 ELEC 6270-001 Low-Power Design of Electronic Circuits 4 Why Level Converters??? VDD_L VDD_H Vin_HVin_L Vout_L Vout_H ( = 2.5 V) ( = 3.3 V) ( ‘0’= 0 V) (‘1’= 3.3V) ( ‘0’= 0 V) (‘1’= 2.5V) (1) (2) ( ‘0’= 0 V) (‘1’= 2.5V) ( ‘0’= ???) (‘1’= 3.3V) So……… only a Low-to-High Level Converter is required!!

5. 11/29/2007 ELEC 6270-001 Low-Power Design of Electronic Circuits 5 Low-to-High Level Converter Vin_L Vout_H VDD_H VDD_L N. H. E. Weste and D. Harris, CMOS VLSI Design, Third Edition, Section 12.4.3, Addison-Wesley, 2005. Transistors with thicker oxide and longer channels n1 n2 p1p2

6. 11/29/2007 ELEC 6270-001 Low-Power Design of Electronic Circuits 6 Adder and Level Converter Design  The 32-bit adder was designed using VHDL  Synthesized with 0.35 micron TSMC technology using Leonardo - Area = 224 gates  Designed the Level Converters using Design Architect  Timing and Power analysis was done using ELDO

7. 11/29/2007 ELEC 6270-001 Low-Power Design of Electronic Circuits 7 Normal (High) Voltage Operation of the Adder V DD = 3.3 V Power Dissipation = 2.1120 miliwatt Delay = 0.55882 ns

8. 11/29/2007 ELEC 6270-001 Low-Power Design of Electronic Circuits 8 Experimental Results VDDL (in Volts) Average Power Delay (in nanosecond) Adder (in miliwatts) Level Converter (in microwatts) 32 - Level Converters (in miliwatts) TOTAL (in miliwatts) 3.01.6123117.71023.77095.50811.51444 2.51.0266126.88474.05965.21501.88333 2.00.63547193.9416.25157.05713.77439 1.50.35897148.5038*4.2706*4.7805*- 1.00.16437128.8465*0.58371*0.7781*- * The power consumption values when the level converter fails

9. 11/29/2007 ELEC 6270-001 Low-Power Design of Electronic Circuits 9 Delay Break-Up VDD in Volts Delay in ns AdderLevel ConverterTotal 3.30.55882(not used)- 3.00.61970.985851.60555 2.50.771.245752.01575 2.0 1.018292.618893.63718 1.5 1.59359Fails- 1.0 5.58529Fails-

10. 11/29/2007 ELEC 6270-001 Low-Power Design of Electronic Circuits 10 Power Versus Voltage Plot for the Adder P α V DD 2

11. 11/29/2007 ELEC 6270-001 Low-Power Design of Electronic Circuits 11 Delay versus Voltage Plot for the Adder = 1.5

12. 11/29/2007 ELEC 6270-001 Low-Power Design of Electronic Circuits 12 Power-Delay Product Plot for the Adder VDD = 1.5V P = 0.359 mW D = 1.59 ns

13. 11/29/2007 ELEC 6270-001 Low-Power Design of Electronic Circuits 13 Reason for High Power Consumption in Level Converter Vin_L Vout_H VDD_H VDD_L n1 n2 p1p2 The p1 – n1 and p2 – n2 transistors stay ON simultaneously for time >= the inverter delay, thus substantial short circuit power dissipation.

14. 11/29/2007 ELEC 6270-001 Low-Power Design of Electronic Circuits 14 Alternative Design of a Level Converter CK Vin_L CK VDD_H Vout_H PhaseCKInputsOutput Prechargelowdon’t carehigh EvaluationhighValid inputs Valid outputs Dynamic CMOS Inverter Inverter Operating at the regular supply voltage (VDD_H) n1 n2 p High Voltage clock

15. 11/29/2007 ELEC 6270-001 Low-Power Design of Electronic Circuits 15 Low Voltage Adder Operation with the Dynamic CMOS based Low-to-High Level Converter VDDL (in Volts) Average Power Delay (in nanosecond) Adder (in miliwatts) Level Converter (in microwatts) 32 - Level Converters (in miliwatts) TOTAL (in miliwatts) 3.01.5596452.03881.88413.83871.28385 2.51.040148.18521.74002.83001.35529 2.00.6999345.60251.63232.5818 1.50.4255943.29081.55672.02881.83406 1.40.3859743.03251.57832.01041.9826 1.00.2721447.20372.14222.46445.41575 ~ 5% reduction in power consumption

16. 11/29/2007 ELEC 6270-001 Low-Power Design of Electronic Circuits 16 Conventional Level Converter Dynamic CMOS based Level Converter Problem with this design too!!  Gives rise to glitches due to the precharge phase of the clock

17. 11/29/2007 ELEC 6270-001 Low-Power Design of Electronic Circuits 17 Conclusion The power consumption of the conventional level converter is too high to be used with the adder for power reduction. Need a one with lesser power consumption. The optimum voltage for a low-voltage operation of the adder was found to be ~ 1.5 V, at which Power consumption = 0.36 mW (a drop of 83% from 2.112 mW at 3.3V ) Delay = 1.594 ns (three times increase from 0.56 ns at 3.3V)

18. 11/29/2007 ELEC 6270-001 Low-Power Design of Electronic Circuits 18 Future Work Investigate the effectiveness of using a level converter based flip flop [1],[2], in order to incorporate the level conversion in the register following the combinational logic. Use of other low power level converters [1].

19. 11/29/2007 ELEC 6270-001 Low-Power Design of Electronic Circuits 19 References Class Lectures N. H. E. Weste and D. Harris, CMOS VLSI Design, Third Edition ELDO User Manual [1] F. Ishihara, F. Sheikh, B. Nikolic, “Level Conversion for Dual-Supply Systems,” in IEEE Transactions on VLSI Systems, Vol. 12, No. 2, Feb. 2004, pp.185–195. [2] F. Klass, “Semi-Dynamic and Dynamic Flip-Flops with Embedded Logic,” in Symposium on VLSI Circuits Digest of Technical Papers, 1998, pp. 108 – 109.

20. 11/29/2007 ELEC 6270-001 Low-Power Design of Electronic Circuits 20 THANK YOU!!!