1. PED Roadmapping Issues Vijaykrishnan Narayanan Dept. of CSE Penn State University GSRC Workshop, March 20-21, 2003

2. GSRC Panel ©. PSU 3/21/03 Why PED-Robustness Roadmap? 1970’s 1980’s 1990’s 2000’s area power speed/areaspeed low power speed/power speed/power/reliability reliable ultra-low power

3. GSRC Panel ©. PSU 3/21/03 Increasing variability Static u Changes in characteristics of devices and wire u Caused by the IC manufacturing process & wear-out. Runtime u Changes in V DD, temperature, V t, local coupling, external noise sources u Caused by runtime variation due to environment/operation.

4. GSRC Panel ©. PSU 3/21/03 Impact on Optimizations u Lack of modeling resources or information flow can transform variability to uncertainty. u Designing for worst case will not be power-efficient u Need for adaptation and dynamic monitoring s Enablers: Modeling of noise sources, Interaction of parameters that can be controlled at runtime, overheads

5. GSRC Panel ©. PSU 3/21/03 Power-Reliability Interaction u Supply voltage fluctuations can increase in power-aware design s Need models that can be adapted by architects/software designers that abstract detailed circuit issues s Cost of hardware solutions - supply grids, decoupling capacitances s Cost of software solutions – balancing work load u Substrate coupling between digital and analog u Interconnect reliability and power s Noise sources – single errors, multiple errors, amplitude of the error sources, modes of failure s Challenge – detecting the unobserved

6. GSRC Panel ©. PSU 3/21/03 Detectable & Residual Word Error Rate

7. GSRC Panel ©. PSU 3/21/03 Dynamic Switching Error Detection Codes

8. GSRC Panel ©. PSU 3/21/03 Power-Reliability Interaction u Supply voltage fluctuations can increase in power-aware design s Need models that can be adapted by architects/software designers that abstract detailed circuit issues s Cost of hardware solutions - supply grids, decoupling capacitances s Cost of software solutions – balancing work load u Substrate coupling between digital and analog u Interconnect reliability and power s Noise sources – single errors, multiple errors, amplitude of the error sources, modes of failure s Challenge – detecting the unobserved s How to offset encoding/decoding costs – Just Enough Power u Soft errors

9. GSRC Panel ©. PSU 3/21/03 Soft Errors in Leakage Controlled SRAMs u Q critical depends on capacitance and voltage and is the key parameter s Leakage controlled circuits are more susceptible to Soft errors u Support for error correction and detection (SECDED) s Specially important for dirty data not written back

10. GSRC Panel ©. PSU 3/21/03 Leakage Vs Soft Error Susceptibility

11. GSRC Panel ©. PSU 3/21/03 Conclusion u Need system approach that spans circuit, micro- architecture, software to addressing problems #1 Create models of physical/circuit effects reusable at higher levels of abstraction – what is important to optimize? #2 How to map applications onto the underlying heterogeneous fabrics to meet energy and reliability requirements? #3 What are new technologies that change slopes of technology trends? #4 Roadmap applications – what does the world need or rather what can we give the world?