1. Memory and Advanced
Digital Circuits 1

2. sedr42021_1101a.jpg
Figure (a) Basic latch. (b) The latch with the feedback loop opened. (c) Determining the operating point(s) of the latch.
Microelectronic Circuits - Fifth Edition Sedra/Smith

3. sedr42021_1102a.jpg
Figure (a) The set/reset (SR) flip-flop and (b) its truth table.
Microelectronic Circuits - Fifth Edition Sedra/Smith

4. sedr42021_1103.jpg
Figure CMOS implementation of a clocked SR flip-flop. The clock signal is denoted by f.
Microelectronic Circuits - Fifth Edition Sedra/Smith

5. sedr42021_1104.jpg
Figure The relevant portion of the flip-flop circuit of Fig for determining the minimum W/L ratios of Q5 and Q6 needed to ensure that the flip-flop will switch.
Microelectronic Circuits - Fifth Edition Sedra/Smith

6. sedr42021_1105.jpg
Figure A simpler CMOS implementation of the clocked SR flip-flop. This circuit is popular as the basic cell in the design of static random-access memory (SRAM) chips.
Microelectronic Circuits - Fifth Edition Sedra/Smith

7. sedr42021_1106.jpg
Figure A block-diagram representation of the D flip-flop.
Microelectronic Circuits - Fifth Edition Sedra/Smith

8. sedr42021_1107a.jpg
Figure A simple implementation of the D flip-flop. The circuit in (a) utilizes the two-phase nonoverlapping clock whose waveforms are shown in (b).
Microelectronic Circuits - Fifth Edition Sedra/Smith

9. sedr42021_1108a.jpg
Figure (a) A master–slave D flip-flop. The switches can be, and usually are, implemented with CMOS transmission gates. (b) Waveforms of the two-phase nonoverlapping clock required.
Microelectronic Circuits - Fifth Edition Sedra/Smith

10. sedr42021_1109.jpg
Figure The monostable multivibrator (one-shot) as a functional block, shown to be triggered by a positive pulse. In addition, there are one shots that are triggered by a negative pulse.
Microelectronic Circuits - Fifth Edition Sedra/Smith

11. sedr42021_1110.jpg
Figure A monostable circuit using CMOS NOR gates. Signal source vI supplies positive trigger pulses.
Microelectronic Circuits - Fifth Edition Sedra/Smith

12. sedr42021_1111a.jpg
Figure (a) Diodes at each input of a two-input CMOS gate. (b) Equivalent diode circuit when the two inputs of the gate are joined together. Note that the diodes are intended to protect the device gates from potentially destructive overvoltages due to static charge accumulation.
Microelectronic Circuits - Fifth Edition Sedra/Smith

13. sedr42021_1112a.jpg
Figure Output equivalent circuit of CMOS gate when the output is (a) low and (b) high.
Microelectronic Circuits - Fifth Edition Sedra/Smith

14. sedr42021_1113a.jpg
Figure Timing diagram for the monostable circuit in Fig
Microelectronic Circuits - Fifth Edition Sedra/Smith

15. sedr42021_1114.jpg
Figure Circuit that applies during the discharge of C (at the end of the monostable pulse interval T).
Microelectronic Circuits - Fifth Edition Sedra/Smith

16. sedr42021_1115a.jpg
Figure (a) A simple astable multivibrator circuit using CMOS gates. (b) Waveforms for the astable circuit in (a). The diodes at the gate input are assumed to be ideal and thus to limit the voltage vI1 to 0 and VDD.
Microelectronic Circuits - Fifth Edition Sedra/Smith

17. sedr42021_1116a.jpg
Figure (a) A ring oscillator formed by connecting three inverters in cascade. (Normally at least five inverters are used.) (b) The resulting waveform. Observe that the circuit oscillates with frequency 1/6tP.
Microelectronic Circuits - Fifth Edition Sedra/Smith

18. sedr42021_1117.jpg
Figure A 2M+N-bit memory chip organized as an array of 2M rows ´ 2N columns.
Microelectronic Circuits - Fifth Edition Sedra/Smith

19. sedr42021_1118.jpg Figure 11.18 A CMOS SRAM memory cell.
Microelectronic Circuits - Fifth Edition Sedra/Smith

20. sedr42021_1119a.jpg
Figure Relevant parts of the SRAM cell circuit during a read operation when the cell is storing a logic 1. Note that initially vQ = VDD and vQ = 0. Also note that the B and B lines are usually precharged to a voltage of about VDD/2. However, in Example 11.2, it is assumed for simplicity that the precharge voltage is VDD.
Microelectronic Circuits - Fifth Edition Sedra/Smith

21. sedr42021_1120a.jpg
Figure Relevant parts of the SRAM circuit during a write operation. Initially, the SRAM has a stored 1 and a 0 is being written. These equivalent circuits apply before switching takes place. (a) The circuit is pulling node Q up toward VDD/2. (b) The circuit is pulling node Q down toward VDD/2.
Microelectronic Circuits - Fifth Edition Sedra/Smith

22. sedr42021_1121.jpg Figure 11.21 The one-transistor dynamic RAM cell.
Microelectronic Circuits - Fifth Edition Sedra/Smith

23. sedr42021_1122.jpg
Figure When the voltage of the selected word line is raised, the transistor conducts, thus connecting the storage capacitor CS to the bit-line capacitance CB.
Microelectronic Circuits - Fifth Edition Sedra/Smith

24. sedr42021_1123.jpg
Figure A differential sense amplifier connected to the bit lines of a particular column. This arrangement can be used directly for SRAMs (which utilize both the B and B lines). DRAMs can be turned into differential circuits by using the “dummy cell” arrangement shown in Fig
Microelectronic Circuits - Fifth Edition Sedra/Smith

25. sedr42021_1124.jpg
Figure Waveforms of vB before and after the activation of the sense amplifier. In a read-1 operation, the sense amplifier causes the initial small increment DV(1) to grow exponentially to VDD. In a read-0 operation, the negative DV(0) grows to 0. Complementary signal waveforms develop on the B line.
Microelectronic Circuits - Fifth Edition Sedra/Smith

26. sedr42021_1125.jpg
Figure An arrangement for obtaining differential operation from the single-ended DRAM cell. Note the dummy cells at the far right and far left.
Microelectronic Circuits - Fifth Edition Sedra/Smith

27. sedr42021_1126.jpg
Figure A NOR address decoder in array form. One out of eight lines (row lines) is selected using a 3-bit address.
Microelectronic Circuits - Fifth Edition Sedra/Smith

28. sedr42021_1127.jpg
Figure A column decoder realized by a combination of a NOR decoder and a pass-transistor multiplexer.
Microelectronic Circuits - Fifth Edition Sedra/Smith

29. sedr42021_1128.jpg
Figure A tree column decoder. Note that the colored path shows the transistors that are conducting when A0 = 1, A1 = 0, and A2 = 1, the address that results in connecting B5 to the data line.
Microelectronic Circuits - Fifth Edition Sedra/Smith

30. sedr42021_1129.jpg
Figure A simple MOS ROM organized as 8 words ´ 4 bits.
Microelectronic Circuits - Fifth Edition Sedra/Smith

31. sedr42021_1130a.jpg
Figure (a) Cross section and (b) circuit symbol of the floating-gate transistor used as an EPROM cell.
Microelectronic Circuits - Fifth Edition Sedra/Smith

32. sedr42021_1131.jpg
Figure Illustrating the shift in the iD–vGS characteristic of a floating-gate transistor as a result of programming.
Microelectronic Circuits - Fifth Edition Sedra/Smith

33. sedr42021_1132.jpg
Figure The floating-gate transistor during programming.
Microelectronic Circuits - Fifth Edition Sedra/Smith

34. sedr42021_1133.jpg
Figure The basic element of ECL is the differential pair. Here, VR is a reference voltage.
Microelectronic Circuits - Fifth Edition Sedra/Smith

35. sedr42021_1134.jpg
Figure Basic circuit of the ECL 10K logic-gate family.
Microelectronic Circuits - Fifth Edition Sedra/Smith

36. sedr42021_e1118.jpg
Figure E11.18
Microelectronic Circuits - Fifth Edition Sedra/Smith

37. sedr42021_1135.jpg
Figure The proper way to connect high-speed logic gates such as ECL. Properly terminating the transmission line connecting the two gates eliminates the “ringing” that would otherwise corrupt the logic signals. (See Section )
Microelectronic Circuits - Fifth Edition Sedra/Smith

38. sedr42021_1136.jpg
Figure Simplified version of the ECL gate for the purpose of finding transfer characteristics.
Microelectronic Circuits - Fifth Edition Sedra/Smith

39. sedr42021_1137.jpg
Figure The OR transfer characteristic vOR versus vI , for the circuit in Fig
Microelectronic Circuits - Fifth Edition Sedra/Smith

40. sedr42021_1138.jpg Figure 11.38 Circuit for determining VOH.
Microelectronic Circuits - Fifth Edition Sedra/Smith

41. sedr42021_1139.jpg
Figure The NOR transfer characteristic, vNOR versus vI , for the circuit in Fig
Microelectronic Circuits - Fifth Edition Sedra/Smith

42. sedr42021_1140.jpg
Figure Circuit for finding, vNOR versus vI for the range vI > VIH.
Microelectronic Circuits - Fifth Edition Sedra/Smith

43. sedr42021_1141.jpg
Figure Equivalent circuit for determining the temperature coefficient of the reference voltage VR .
Microelectronic Circuits - Fifth Edition Sedra/Smith

44. sedr42021_1142.jpg
Figure Equivalent circuit for determining the temperature coefficient of VOL.
Microelectronic Circuits - Fifth Edition Sedra/Smith

45. sedr42021_1143.jpg
Figure Equivalent circuit for determining the temperature coefficient of VOH.
Microelectronic Circuits - Fifth Edition Sedra/Smith

46. sedr42021_1144.jpg Figure 11.44 The wired-OR capability of ECL.
Microelectronic Circuits - Fifth Edition Sedra/Smith

47. sedr42021_1145a.jpg
Figure Development of the BiCMOS inverter circuit. (a) The basic concept is to use an additional bipolar transistor to increase the output current drive of each of QN and QP of the CMOS inverter. (b) The circuit in (a) can be thought of as utilizing these composite devices.
Microelectronic Circuits - Fifth Edition Sedra/Smith

48. sedr42021_1145c.jpg
Figure (Continued) (c) To reduce the turn-off times of Q1 and Q2, “bleeder resistors” R1 and R2 are added. (d) Implementation of the circuit in (c) using NMOS transistors to realize the resistors. (e) An improved version of the circuit in (c) obtained by connecting the lower end of R1 to the output node.
Microelectronic Circuits - Fifth Edition Sedra/Smith

49. sedr42021_1146a.jpg
Figure Equivalent circuits for charging and discharging a load capacitance C. Note that C includes all the capacitances present at the output node.
Microelectronic Circuits - Fifth Edition Sedra/Smith

50. sedr42021_1147.jpg Figure 11.47 A BiCMOS two-input NAND gate.
Microelectronic Circuits - Fifth Edition Sedra/Smith

51. sedr42021_1148.jpg
Figure Capture schematic of the two-input ECL gate for Example 11.5.
Microelectronic Circuits - Fifth Edition Sedra/Smith

52. sedr42021_1149.jpg
Figure Circuit arrangement for computing the voltage transfer characteristics of the ECL gate in Fig
Microelectronic Circuits - Fifth Edition Sedra/Smith

53. sedr42021_1150.jpg
Figure Voltage transfer characteristics of the OR and NOR outputs (see Fig ) for the ECL gate shown in Fig Also indicated is the reference voltage, VR = –1.32 V.
Microelectronic Circuits - Fifth Edition Sedra/Smith

54. sedr42021_1151a.jpg
Figure Comparing the voltage transfer characteristics of the OR and NOR outputs (see Fig ) of the ECL gate shown in Fig , with the reference voltage VR generated using: (a) the temperature-compensated bias network of Fig
Microelectronic Circuits - Fifth Edition Sedra/Smith

55. sedr42021_1151b.jpg
Figure (Continued) (b) a temperature-independent voltage source.
Microelectronic Circuits - Fifth Edition Sedra/Smith

56. sedr42021_1152.jpg
Figure Circuit arrangement for investigating the dynamic operation of ECL. Two ECL gates (Fig ) are connected in cascade via a 1.5-m coaxial cable which has a characteristic impedance Z0 = 50 W and a propagation delay td = 10 ns. Resistor RT1 (50 W) provides proper termination for the coaxial cable.
Microelectronic Circuits - Fifth Edition Sedra/Smith

57. sedr42021_1153.jpg
Figure Transient response of a cascade of two ECL gates interconnected by a 1.5-m coaxial cable having a characteristic impedance of 50 W and a delay of 10 ns (see Fig ).
Microelectronic Circuits - Fifth Edition Sedra/Smith

58. sedr42021_1154.jpg
Figure Transient response of a cascade of two ECL gates interconnected by a 1.5-m cable having a characteristic impedance of 300 W. The termination resistance RT1 (see Fig ) was kept unchanged at 50 W. Note the change in time scale of the plot.
Microelectronic Circuits - Fifth Edition Sedra/Smith

59. sedr42021_p1140.jpg
Figure P11.40
Microelectronic Circuits - Fifth Edition Sedra/Smith

60. sedr42021_p1150.jpg
Figure P11.50
Microelectronic Circuits - Fifth Edition Sedra/Smith