1. Fall 2006, Oct. 17 ELEC 5270-001/6270-001 Lecture 9 1 ELEC 5270-001/6270-001(Fall 2006) Low-Power Design of Electronic Circuits Power Analysis: Logic Level Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu

2. Fall 2006, Oct. 17ELEC 5270-001/6270-001 Lecture 92 Power Analysis Motivation: Motivation: Specification Specification Optimization Optimization Reliability Reliability Applications Applications Design analysis and optimization Design analysis and optimization Physical design Physical design Packaging Packaging Test Test

3. Fall 2006, Oct. 17ELEC 5270-001/6270-001 Lecture 93 Abstraction, Complexity, Accuracy Abstraction level Computing resources Analysis accuracy AlgorithmLeastWorst Software and system Hardware behavior Register transfer Logic Circuit DeviceMostBest

4. Fall 2006, Oct. 17ELEC 5270-001/6270-001 Lecture 94 Spice Circuit/device level analysis Circuit/device level analysis Circuit modeled as network of transistors, capacitors, resistors and voltage/current sources. Circuit modeled as network of transistors, capacitors, resistors and voltage/current sources. Node current equations using Kirchhoff’s current law. Node current equations using Kirchhoff’s current law. Average and instantaneous power computed from supply voltage and device current. Average and instantaneous power computed from supply voltage and device current. Analysis is accurate but expensive Analysis is accurate but expensive Used to characterize parts of a larger circuit. Used to characterize parts of a larger circuit. Original references: Original references: L. W. Nagel and D. O. Pederson, “SPICE – Simulation Program With Integrated Circuit Emphasis,” Memo ERL-M382, EECS Dept., University of California, Berkeley, Apr. 1973. L. W. Nagel and D. O. Pederson, “SPICE – Simulation Program With Integrated Circuit Emphasis,” Memo ERL-M382, EECS Dept., University of California, Berkeley, Apr. 1973. L. W. Nagel, SPICE 2, A Computer program to Simulate Semiconductor Circuits, PhD Dissertation, University of California, Berkeley, May 1975. L. W. Nagel, SPICE 2, A Computer program to Simulate Semiconductor Circuits, PhD Dissertation, University of California, Berkeley, May 1975.

5. Fall 2006, Oct. 17ELEC 5270-001/6270-001 Lecture 95 CaCa Logic Model of MOS Circuit CcCc CbCb V DD a b c pMOS FETs nMOS FETs C a, C b, C c and C d are node capacitances DcDc DaDa c a b D a and D b are interconnect or propagation delays D c is inertial delay of gate DbDb CdCd

6. Fall 2006, Oct. 17ELEC 5270-001/6270-001 Lecture 96 Spice Characterization of a 2-Input NAND Gate Input data pattern Delay (ps) Dynamic energy (pJ) a = b = 0 → 1 a = b = 0 → 1691.55 a = 1, b = 0 → 1 a = 1, b = 0 → 1621.67 a = 0 → 1, b = 1 a = 0 → 1, b = 1501.72 a = b = 1 → 0 351.82 a = 1, b = 1 → 0 761.39 a = 1 → 0, b = 1 571.94

7. Fall 2006, Oct. 17ELEC 5270-001/6270-001 Lecture 97 Spice Characterization (Cont.) Input data pattern Static power (pW) a = b = 0 a = b = 05.05 a = 0, b = 1 a = 0, b = 113.1 a = 1, b = 0 5.10 a = b = 1 28.5

8. Fall 2006, Oct. 17ELEC 5270-001/6270-001 Lecture 98 Switch-Level Partitioning Circuit partitioned into channel-connected components for Spice characterization. Circuit partitioned into channel-connected components for Spice characterization. Reference: R. E. Bryant, “A Switch-Level Model and Simulator for MOS Digital Systems,” IEEE Trans. Computers, vol. C-33, no. 2, pp. 160-177, Feb. 1984. Reference: R. E. Bryant, “A Switch-Level Model and Simulator for MOS Digital Systems,” IEEE Trans. Computers, vol. C-33, no. 2, pp. 160-177, Feb. 1984. G1G1 G2G2 G3G3 Internal switching nodes not seen by logic simulator

9. Fall 2006, Oct. 17ELEC 5270-001/6270-001 Lecture 99 Delay and Discrete-Event Simulation (NAND gate) b a c (CMOS) Time units 0 5 c (zero delay) c (unit delay) c (multiple delay) c (minmax delay) Inputs Logic simulation min =2, max =5 rise=5, fall=5 Transient region Unknown (X) X

10. Fall 2006, Oct. 17ELEC 5270-001/6270-001 Lecture 910 Event-Driven Simulation (Example) 2 2 4 2 a =1 b =1 c =1→0 d = 0 e =1 f =0 g =1 Time, t 0 4 8 g t = 0 1 2 3 4 5 6 7 8 Scheduled events c = 0 d = 1, e = 0 g = 0 f = 1 g = 1 Activity list d, e f, g g Time stack

11. Fall 2006, Oct. 17ELEC 5270-001/6270-001 Lecture 911 Time Wheel (Circular Stack) t=0 1 2 3 4 5 6 7 max Current time pointer Event link-list

12. Fall 2006, Oct. 17ELEC 5270-001/6270-001 Lecture 912 Gate-Level Power Analysis Pre-simulation analysis: Pre-simulation analysis: Partition circuit into channel connected gate components. Partition circuit into channel connected gate components. Determine node capacitances from layout analysis (accurate) or from wire-load model* (approximate). Determine node capacitances from layout analysis (accurate) or from wire-load model* (approximate). Determine dynamic and static power from Spice for each gate. Determine dynamic and static power from Spice for each gate. Determine gate delays using Spice or Elmore delay analysis. Determine gate delays using Spice or Elmore delay analysis. * Wire-load model estimates of a net by its pin-count. See Yeap, p. 39.

13. Fall 2006, Oct. 17ELEC 5270-001/6270-001 Lecture 913 Elmore Delay Model W. Elmore, “The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers,” J. Appl. Phys., vol. 19, no.1, pp. 55-63, Jan. 1948. W. Elmore, “The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers,” J. Appl. Phys., vol. 19, no.1, pp. 55-63, Jan. 1948. s 1 2 3 4 5 R1 R2 R3 R4 R5 C1 C2 C3 C5 C4 Shared resistance: R45 = R1 + R3 R15 = R1 R34 = R1 + R3

14. Fall 2006, Oct. 17ELEC 5270-001/6270-001 Lecture 914 Elmore Delay Formula N Delay at node k= 0.69Σ Cj × Rjk j=1 where N = number of capacitive nodes in the network Example: Delay at node 5= 0.69[R1 C1 + R1 C2 + (R1+R3)C3 + (R1+R3)C4 (R1+R3+R5)C5]

15. Fall 2006, Oct. 17ELEC 5270-001/6270-001 Lecture 915 Gate-Level Power Analysis (Cont.) Run discrete-event (event-driven) logic simulation with a set of input vectors. Run discrete-event (event-driven) logic simulation with a set of input vectors. Monitor the toggle count of each net and obtain capacitive power dissipation: Monitor the toggle count of each net and obtain capacitive power dissipation: P cap = Σ C k V 2 f all nodes k all nodes k Where: Where: C k is the total node capacitance being switched, as determined by the simulator. C k is the total node capacitance being switched, as determined by the simulator. V is the supply voltage. V is the supply voltage. f is the clock frequency, i.e., the number of vectors applied per unit f is the clock frequency, i.e., the number of vectors applied per unit

16. Fall 2006, Oct. 17ELEC 5270-001/6270-001 Lecture 916 Gate-Level Power Analysis (Cont.) Monitor dynamic energy events at the input of each gate and obtain internal switching power dissipation: Monitor dynamic energy events at the input of each gate and obtain internal switching power dissipation: P int = Σ Σ E(g,e) f(g,e) gates g events e gates g events e Where Where E(g,e) = energy of event e of gate g pre-computed from Spice. E(g,e) = energy of event e of gate g pre-computed from Spice. F(g,e) = occurrence frequency of the event e at gate g observed by logic simulation. F(g,e) = occurrence frequency of the event e at gate g observed by logic simulation.

17. Fall 2006, Oct. 17ELEC 5270-001/6270-001 Lecture 917 Gate-Level Power Analysis (Cont.) Monitor the static power dissipation state of each gate and obtain the static power dissipation: Monitor the static power dissipation state of each gate and obtain the static power dissipation: P stat = ΣΣ P(g,s) T(g,s)/ T gates g states s gates g states s Where Where P(g,s) = static power dissipation of gate g for state s, obtained from Spice. P(g,s) = static power dissipation of gate g for state s, obtained from Spice. T(g,s) = duration of state s at gate g, obtained from logic simulation. T(g,s) = duration of state s at gate g, obtained from logic simulation. T = vector period. T = vector period.

18. Fall 2006, Oct. 17ELEC 5270-001/6270-001 Lecture 918 Gate-Level Power Analysis (Cont.) Sum up all three components of power: Sum up all three components of power: P = P cap + P int + P stat References: References: A. Deng, “Power Analysis for CMOS/BiCMOS Circuits,” Proc. International Workshop Low Power Design, 1994. A. Deng, “Power Analysis for CMOS/BiCMOS Circuits,” Proc. International Workshop Low Power Design, 1994. J. Benkoski, A. C. Deng, C. X. Huang, S. Napper and J. Tuan, “Simulation Algorithms, Power Estimation and Diagnostics in PowerMill,” Proc. PATMOS, 1995. J. Benkoski, A. C. Deng, C. X. Huang, S. Napper and J. Tuan, “Simulation Algorithms, Power Estimation and Diagnostics in PowerMill,” Proc. PATMOS, 1995. C. X. Huang, B. Zhang, A. C. Deng and B. Swirski, “The Design and Implementation of PowerMill,” Proc. International Symp. Low Power Design, 1995, pp. 105-109. C. X. Huang, B. Zhang, A. C. Deng and B. Swirski, “The Design and Implementation of PowerMill,” Proc. International Symp. Low Power Design, 1995, pp. 105-109.