1. S. Reda EN1600 SP’08 Design and Implementation of VLSI Systems (EN1600) Lecture 24: Computer-Aided Design using Tanner Tools Prof. Sherief Reda Division of Engineering, Brown University Spring 2008

2. S. Reda EN1600 SP’08 S-Edit: A tool for schematic entry

3. S. Reda EN1600 SP’08 Add a library (SCMOS) to your design

4. S. Reda EN1600 SP’08 The library content (cells show up)

5. S. Reda EN1600 SP’08 Add a view to your design

6. S. Reda EN1600 SP’08 You can draw your circuit in the view canvas

7. S. Reda EN1600 SP’08 How to add components to the view?

8. S. Reda EN1600 SP’08 Create an input port

9. S. Reda EN1600 SP’08 Create busses (bundles) Wire (net) Wire (net) label

10. S. Reda EN1600 SP’08 Then label the individual wires and the buses

11. S. Reda EN1600 SP’08 Repeat for other signals. Make sure to label the input/output pads correctly Check your schematic

12. S. Reda EN1600 SP’08 Export your netlist

13. S. Reda EN1600 SP’08 Switch to L-Edit Load the setup and library

14. S. Reda EN1600 SP’08 P & R setup

15. S. Reda EN1600 SP’08 Then P & R

16. S. Reda EN1600 SP’08 Everything gets done for you! Where are the pins?

17. S. Reda EN1600 SP’08 Make things easier by specifying pin locations

18. S. Reda EN1600 SP’08 Redo P & R → the IO pads to the boundary You can extract to SPICE and continue as usual

19. S. Reda EN1600 SP’08 Hierarchical design in S-Edit Create a symbol out of your register schematic

20. S. Reda EN1600 SP’08 Now create a new view schematic in your design (slide 5)

21. S. Reda EN1600 SP’08 Start adding your registers as instances

22. S. Reda EN1600 SP’08 Then interconnect your placed components

23. S. Reda EN1600 SP’08 Now P & R the whole thing

24. S. Reda EN1600 SP’08 Overall flow Schematic capture using S-Edit P & R using L-Edit Cell library SPICE IC layout/ area Verification timing/ power design entry

25. Final project Your project should fit on a 1.5 x 1.5 mm 40-pin MOSIS “TinyChip” fabricated in a 0.5 µm AMI process  your project must not exceed 5000 x 5000 λ including I/O pads. Therefore, the core of your project must fit in a 3400 x 3400 λ box and have no more than 40 pins. Six pins should be dedicated to VDD/GND, so only 34 are available as I/Os. Fabrication schedule is 6 th of June. Only projects that have demonstrated to work perfectly have a chance to get fabricated. Chips come during the Fall so you have to commit to testing them when they come back. We might be limited to one design submission, so priority will be given to projects that are perfect (DRC is 100% OK, electrical verification is 100% OK, etc). S. Reda EN1600 SP’08

26. Project logistics There is a project report and presentation per group at the last lecture of the semester (5/5). Class project is worth 20% of your grade. You are allowed to work in groups of 2 or 3. –Grading: 15% specification 20% design schematics 10% layout 30% verification and SPICE simulations 10% final report organization 15% presentation S. Reda EN1600 SP’08

27. Class project suggestions and milestones Possible projects: small programmable FPGA, cache memory, error detection and correction circuits, a small CPU, digital signal processing circuits, high speed arithmetic circuits, etc. Milestones: –Wed April 9: Team and project finalization –Wed April 16: Specifications for your project well documents (block diagrams, functionality specification using pseudo-code or C/MATLAB, I/O pads, chip area estimation, etc) –Wed April 23: schematics and layouts are finalized –Wed April 30: simulations and verification is finalized –Mon May 5: Report and final presentation S. Reda EN1600 SP’08