1. Chapter 4 I/O Port Programming

2. Objective 我們要瞭解 8051 的各個腳位（pins）的意義與用法，才能知道 8051 是如何與外界溝通。
8051 的一些特別的 pins：Vcc, GND, XTAL1...。這一部份，舊版的課本在第4.1節，新版的課本在第8.1節，還有一些資訊可以在Appendix中找到。
其中8051 提供 4 組 I/O ports：P0～P3 以對外送出資料與接收資料。這一部份在這裡會詳細說明，我們應如何寫程式控制 I/O ports。
利用 Appendix C 可以瞭解如何控制 8051 的 I/O ports，以及為什麼寫程式時需要某些限制。

3. Connecting to LEDs (as an Output)
74LS244 是一個 tri-state buffer, 未設定時為 high-impedence.

4. Sections
I/O programming
4.2 I/O bit manipulation programming

5. Section 4.1 Pin Description of the 8051

6. Pins of 8051 Figure 4-1. 8051 Pin Diagram
The 8051 family members all have 40 pins.
Vcc, GND, XTAL1, XTAL2,... (See Chapter 8).
I/O port pins
The four ports: Port 0, Port 1, Port 2, and Port 3
Usually we call them as P0, P1, P2, and P3.
Each port uses 8 pins.
They are all bit-addressable.

7. Figure 4-1. 8051 Pin Diagram 8051 (8031) PDIP/Cerdip 1 2 3 4 5 6 7 8 910 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
(RXD)P3.0
(TXD)P3.1
(T0)P3.4
(T1)P3.5
XTAL2
XTAL1
GND
(INT0)P3.2
(INT1)P3.3
(RD)P3.7
(WR)P3.6
Vcc
P0.0(AD0)
P0.1(AD1)
P0.2(AD2)
P0.3(AD3)
P0.4(AD4)
P0.5(AD5)
P0.6(AD6)
P0.7(AD7)
EA/VPP
ALE/PROG
PSEN
P2.7(A15)
P2.6(A14)
P2.5(A13)
P2.4(A12)
P2.3(A11)
P2.2(A10)
P2.1(A9)
P2.0(A8)
8051
(8031)

8. Table 4-3: Single-Bit Addressability of Ports
Port Bit P3 P2 P1 P0

9. Pins of I/O Port The 8051 has four I/O ports
Port 0 （pins 32-39）：P0（P0.0～P0.7）
Port 1（pins 1-8）：P1（P1.0～P1.7）
Port 2（pins 21-28）：P2（P2.0～P2.7）
Port 3（pins 10-17）：P3（P3.0～P3.7）
Each port has 8 pins. It is bit-addressable.
Named P0.X , P1.X, P2.X, P3.X（X=0,1,...,7）
P0.0 is the bit 0（LSB）of P0
P0.7 is the bit 7（MSB）of P0
These 8 bits form a byte.
Note that 8 pins of port can work independently.
Each port can be used as input or output (bi-direction).
Program is to read data from P0 and then send data to P1

10. Port 1（Pins 1-8） Port 1 is denoted by P1.
P1.0 ~ P1.7
The hardware structure of a pin of P1 is shown in Figure C-10. See page 577.
Every pin has an internal D-latch to store its value. (We will discuss it later) 
We use P1 as examples to show the operations on ports.
P1 as an input port (i.e., read data from external pins)
P1 as an output port (i.e., send data to pins finally)
通常大部份的狀況, port 不是當 output (ex: 接 LED, LCD, 揚聲器), 就是當 input (ex: 接 switch, keyboard, sensor). 就算像 P0 同時是 address 與 data bus, 在同一時間也不會同時是 input 與 output.

11. Port 1 as Output（Write to Port 1）
Send data to Port 1：
MOV A,#55H
BACK: MOV P1,A
ACALL DELAY
CPL A
SJMP BACK
This program let P1 toggle.
You can write to P1 directly.
當 P1 當 output pin 時, P1 的用法就與一般的 register 類似.
CPL A is valid, CPL P1.0 is valid, but CPL P1 is invalid. 所以在上面範例中, 不可以直接將 P1 做 complement.
對於指令 CPL A 組譯後為 F4 ; 會把 A 做 complement.
對於指令 CPL P1.1 組譯後為 B2 91 (使用的是 CPL bit-addr. 的指令), 會把 P1.1 (bit address 為 91) 做 complement.
對於指令 CPL P1 組譯後為 B2 90 ; 執行時會把 90 解讀為 P1.0 (i.e., CPL P1.0), 就會把 P1.0 做 complement.

12. Port 1 as Output（Read-Modify-Write）
Send data to Port 1 after a specific operation is performed on this port.
The sequence of actions taken：
1. CPU reads the latches of the port (not from external pins)
2. CPU perform the operation
3. Modifying the latches
4. Writing to the pins
Note that 8 pins of P1 work independently.
All read-modify-write instructions use the ports as the destination operand.
That is, these ports are configured as output ports.

13. Table 4-6：Read-Modify-Write Instructions
Mnemonics
Example
SETB P1.4
SETB PX.Y
CLR P1.3
CLR PX.Y
MOV P1.2,C
MOV PX.Y, C
DJNZ P1,TARGET
DJNZ PX, TARGET
INC P1
INC PX
CPL P1.2
CPL PX.Y
JBC P1.1, TARGET
JBC PX.Y, TARGET
XRL P1,A
XRL PX
ORL P1,A
ORL PX
ANL P1,A
ANL PX
DEC P1
DEC PX
This table is Table C-6.
ANL: Latch data AND with A , then save back to latch and write to the external pin
ORL: OR XRL: XOR
JBC: jump to TARGET if bit set and clear bit
CPL: complement
INC: increase DEC: decrease
DJNZ: decrease P1 and jump if P1 not zero
MOV the latch value to carry
CLR: clear bit, SETB: set bit
X for 0~3
Y for 0~7

14. Read from Latch（Port 1 as Output Port）(1/2)
To toggle P1 sequentially
MOV P1,#55H ;P1= B
AGAIN: XRL P1,#0FFH ;P1=XOR(P1,0FFH)
ACALL DELAY
SJMP AGAIN
XLR P1,#0FFH performs an exclusion-OR operation on P1 with B.
P1: 55H - 0AAH – 55H – 0AAH
1. Read from the internal latch
2. XOR (P1, 0FFH).
3. Modify the latch.
4. Write to pin

15. Read from Latch（Port 1 as Output Port）(2/2)
AND P1 with A
MOV P1,#55H ;P1= B
MOV A,#0FH ;A = B
ANL P1,A ;P1=AND(P1,0FFH)=05H
The operation of ANL P1,A
1. The instruction reads the internal latch of the port and brings that data into the CPU.
2. The data is ANDed with the contents of register A.
3. The result is rewritten back to the port latch.
4. The port pin data is changed and now has the same value as the port latch.

16. Port 1 as Input Port（Read from Pin ）
Reading high/low signals from external pins
To read correct signals from pins, the latches of port must be set before reading pins
MOV A,#0FFH ;A= B
MOV P1,A ;make P1 an input port
BACK: MOV A,P1 ;get data from P1
MOV P2,A ;send data to P2
SJMP BACK
Readers must study and understand the material on the internal working of ports in Appendix C.2.
To be an input port, P0, P1, P2 and P3 have similar methods.
port 當 input, ex: 接 switch, keyboard, 從 external pin 讀資料進來.
Program is to read data from P0 and then send data to P1

17. Table 4-5: Instructions For Reading an Input Port
Following are instructions for reading external pins of ports:
Mnemonics
Examples
Description
MOV A,PX
MOV A,P2
Bring into A the data at P2 pins
JNB PX.Y,..
JNB P2.1,TARGET
Jump if pin P2.1 is low
JB PX.Y,..
JB P1.3,TARGET
Jump if pin P1.3 is high
MOV C,PX.Y
MOV C,P2.4
Copy status of pin P2.4 to CY

18. Checking an Input Bit
To monitor a bit and make a decision depending on where it is 0 or 1
JB bit,target ; jump if bit set
HERE: JB P2.1,HERE ;jump to HERE if P2.1=1
JNB bit,target ; jump if bit not set
HERE: JNB P2.1,HERE;jump to HERE if P2.1=0
It’s better then JB.
We must set the bit first: SETB P2.1.
See Examples 4-3, 4-4 and 4-5

19. Read Operations on P1 When reading ports, there are two possibilities：
Read the input pin to CPU (from external pin value)
MOV A, P1
JNB P2.1, TARGET ; jump if P2.1 is not set
JB P2.1, TARGET ; jump if P2.1 is set
Table 4-5 instructions to read external pins
Figures C-11, C-12 (page 577)
Read the internal latch (and then output).
ANL P1, A ; P1 ← P1 AND A
ORL P1, A ; P1 ← P1 OR A
INC P ; increase P1
Table 4-6 Read-Modify-Write Instruction
Figure C-17 (page 580)
Note that MOV A,P1 中 P1 讀入 CPU, 但不會寫入 latch 中. 因此 Write to latch =0.
Simulator 設定 P1 的值會把 latch 的值改掉是不對的, 在 8051 chip 中不會有這樣的狀況. 因此在使用 JB, JNB 時, 不需要每次都去設定 P1.X=1, 只要設一次就好了.

20. A Pin of Port 1 P1 P0.x 8051 IC Read latch Vcc TB2 Load(L1) P1.X pin
D Q
Clk Q
Vcc
Load(L1)
Read latch
Read pin
Write to latch
Internal CPU bus M1
P1.X pin
P1.X
TB1
TB2
P1
P0.x
8051 IC

21. Hardware Structure of I/O Pin
Each pin of I/O ports
Internal CPU bus：communicate with CPU
A D latch stores the value of this pin
D latch is controlled by “Write to latch”
Write to latch＝1：write data into the D latch
2 Tri-state buffer：
TB1: controlled by “Read pin”
Read pin＝1 (TB1=1)：really read the data present at the pin
TB2: controlled by “Read latch”
Read latch＝1 (TB2=1)：read value from internal latch
A transistor M1 gate 
Gate=0: output=1
Gate=1: output=0

22. Figure C-9. Tri-state Buffer
Output
Input
Tri-state control (active high) L L H H
Low
High-impedance (open-circuit) H H 

23. Figure C-2 One Transistor Inverter with Pull-Up resistor
The transistor plays the role of a switch.
Transistor can be bipolar or MOS (metal-oxide semiconductor)
Input=1: Vout=Low Input=0: Vout=High
Rc: pull-up resistor
drain
gate
Transistor is on.
Transistor is off.
Transistor
by MOS
source 

24. Writing “1” to Output Pin P1.X
D Q
Clk Q
Vcc
Load(L1)
Read latch
Read pin
Write to latch
Internal CPU bus M1
P1.X pin
P1.X
TB2
2. output pin is Vcc
1. write a 1 to the pin 1
output 1
write to latch=1
TB1
8051 IC

25. Writing “0” to Output Pin P1.X
D Q
Clk Q
Vcc
Load(L1)
Read latch
Read pin
Write to latch
Internal CPU bus M1
P1.X pin
P1.X
TB2
2. output pin is ground
1. write a 0 to the pin
output 0 1
write to latch=1
TB1
8051 IC

26. Figure C-11. Reading “High” at Input Pin
D Q
Clk Q
Vcc
Load(L1)
Read latch
Read pin
Write to latch
Internal CPU bus M1
P1.X pin
P1.X
2. MOV A,P1
external pin=High
TB2
write a 1 to the pin MOV P1,#0FFH 1 1
Note that MOV A,P1 中 P1 讀入 CPU, 但不會寫入 latch 中. 因此 Write to latch =0.
TB1
3. TB1=1 TB2=0 Write to latch=0 Write to CPU =1
8051 IC

27. Figure C-12. Reading “Low” at Input Pin
D Q
Clk Q
Vcc
Load(L1)
Read latch
Read pin
Write to latch
Internal CPU bus M1
P1.X pin
P1.X
2. MOV A,P1
external pin=Low
TB2
write a 1 to the pin
MOV P1,#0FFH 1
TB1
3. TB1=1 TB2=0 Write to latch=0 Write to CPU=1
8051 IC

28. Reading Latch Exclusive-or the Port 1： MOV P1,#55H ;P1=01010101
ORL P1,#0F0H ;P1=
1. The read latch activates TB2 and bring the data from the Q latch into CPU.
Read P1.0=0
2. CPU performs an operation.
This data is ORed with bit 1 of register A. Get 1.
3. The latch is modified.
D latch of P1.0 has value 1.
4. The result is written to the external pin.
External pin (pin 1: P1.0) has value 1.

29. Figure C-17. Reading the Latch (1/2)
1. TB1=0 TB2= Write to latch=0 (Assume P1.X=0 initially)
D Q
Clk Q
Vcc
Load(L1)
Read latch
Read pin
Write to latch
Internal CPU bus M1
P1.X pin
P1.X
TB2
2. CPU compute P1.X OR 1
4. P1.X=1 1 1 1
3. write result to latch Write to latch=1
TB1
8051 IC

30. Figure C-17. Reading the Latch (2/2)
1. TB1=0 TB2= Write to latch=0 (Assume P1.X=0 initially)
D Q
Clk Q
Vcc
Load(L1)
Read latch
Read pin
Write to latch
Internal CPU bus M1
P1.X pin
P1.X
TB2
2. CPU compute P1.X OR 0
4. P1.X=0 1
3. write result to latch Write to latch=1
TB1
8051 IC

31. Other Pins P1, P2, and P3 have internal pull-up resisters.
P1, P2, and P3 are not open drain.
P0 has no internal pull-up resistors and does not connects to Vcc inside the 8051.
P0 is open drain.
Compare the figures of P1.X and P0.X.
However, for a programmer, it is the same to program P0, P1, P2 and P3.
All the ports upon RESET are configured as input.
The initial value of P0, P1, P2 and P3 are FFH.

32. No internal pull-up resistor
A Pin of Port 0
D Q
Clk Q
Read latch
Read pin
Write to latch
Internal CPU bus M1
P0.X pin
P1.X
TB1
TB2
No internal pull-up resistor
open drain
P1.x
8051 IC

33. Port 0（pins 32-39） P0 is an open drain.
Open drain is a term used for MOS chips in the same way that open collector is used for TTL chips.
When P0 is used for simple data I/O we must connect it to external pull-up resistors. 
Each pin of P0 must be connected externally to a 10K ohm pull-up resistor. Then P0 can be an input or output port.
In an 8031-based system, P0 are used to provide address A0-A7 and data D0-D7. (See Chapter 14) 
P0 is connect 74LS373 to latch the address, there is no need for external pull-up resistors.
Open drain is a term used for MOS chips in the same way that open collector is used for TTL chips.

34. Figure 4-4. Port 0 with Pull-Up Resistors
DS5000
8751
8951
Vcc
10 K
Port 0 

35. Port 0 as Address/Data Bus
Figure 14– Connection to External Program ROM

36. Port 0 as Output（Send to the Port）
In order to make P0 an output, we don’t need to do anything.
BACK: MOV A,#55H ;A= B
MOV P0,A ;Send A to P0
ACALL DELAY ;Call procedure DELAY
MOV A,#0AAH ;A= B
SJMP BACK
Program is to read data from P0 and then send data to P1

37. Port 0 as Input（Read from Port）
In order to make P0 an input, the port must be programmed by writing 1 to all the bit.
MOV A,#0FFH ;A= B
MOV P0,A ;make P1 an input port
;by writing all 1s to it
MOV A,P0 ;get data from P0
MOV P1,A ;send data to P1
To be an input port, P0, P1, P2 and P3 have similar methods.
Program is to read data from P0 and then send data to P1

38. Port 2（pins 21-28）
Port 2 does not need any pull-up resistors since it already has pull-up resistors internally.
In an 8031-based system, P2 are used to provide address A8-A15. (See Chapter 14)

39. Port 3（pins 10-17）
Port 3 does not need any pull-up resistors since it already has pull-up resistors internally.
Although port 3 is configured as an output port upon reset, this is not the way it is most commonly used.
Port 3 has the additional function of providing signals.
Serial communications signal：RxD, TxD（Chapter 10）
External interrupt：/INT0, /INT1（Chapter 11）
Timer/counter：T0, T1（Chapter 9）
External memory accesses in 8031-based system：/WR, /RD（Chapter 14）
對8051而言, P3.6 P3.7 用於 I/O, 而其他的 pin 就用於特殊的功能.

40. Table 4-1: Port 3 Alternate Functions17 RD
P3.7 16 WR
P3.6 15 T1
P3.5 14 T0
P3.4 13
INT1
P3.3 12
INT0
P3.2 11
TxD
P3.1 10
RxD
P3.0
Pin
Function
P3 Bit

41. Example 4-1 (1/2)
Write a test program for the DS89C420/30 chip to toggle all the bits of P0, P1, and P2 every ¼ of a second. Assume a crystal frequency of MHz.
Solution:
ORG 0
BACK: MOV A,#55H
MOV P0,A
MOV P1,A
MOV P2,A
ACALL QSDELAY ;QSDELAY is for
MOV A,#0AAH ; 1/4 a second delay
ACALL QSDELAY
SJMP BACK
A= B
A= B

42. Example 4-1 (2/2) QSDELAY: MOV R5,#11 H3: MOV R4,#248 H2: MOV R3,#255
H1: DJNZ R3,H1
DJNZ R4,H2
DJNZ R5,H3
RET
END
Note：
For DS89C4x0, DJNZ needs 4 MCs and one MC needs 90ns.
DELAY=112482554MC90ns=250,430ms

43. I/O Programming To toggle every bit of P1 continuously.
3 ways：Way 1, Way 2, and Way 3.
Which one is better？

44. Way 1 Send data to Port 1 through ACC： BACK: MOV A,#55H ;A=01010101B
MOV P1,A
ACALL DELAY
MOV A,#0AAH ;A= B
SJMP BACK
MOV A,#55H
BACK: MOV P1,A
ACALL DELAY
CPL A
SJMP BACK

45. Way 2 Access Port 1 directly： BACK: MOV P1,#55H ;P1=01010101B
ACALL DELAY
MOV P1,#0AAH ;P1= B
SJMP BACK

46. Way 3 Read-modify-write feature： MOV P1,#55H ;P1=01010101B
AGAIN: XRL P1,#0FFH
ACALL DELAY
SJMP AGAIN
The instruction XRL P1,#0FFH do P1=XOR( P1, FFH）（That is, to toggle P1.）

47. Section 4.2 I/O Bit Manipulation Programming

48. Bit-addressability (1/2)
In most microprocessors, data is accessed in byte-sized chunks.
However, in many applications we need to change one bit, for example, to turn on or off a device.
The bit-addressability of the 8051
The ability to access data in single bit instead of the whole byte.
We can assess any single bit of a port without altering the rest.
Make 8051 become one of the most powerful 8-bit microprocessors.

49. Bit-addressability (2/2)
Which portions of the microprocessor, RAM, registers, I/O ports, or ROM are bit-addressable?
RAM: bit-addressable RAM (20H-2FH) (Chapters 2 & 5)
Register: some of them are bit-addressable (Chapter 5)
Special Function Registers (SFR)
Only registers PSW, A, B, IP, IE, SCON, TCON are bit-addressable.
I/O: all ports are bit-addressable (Chapter 4)
P0, P1, P2, P3
ROM holds program code for executions. There is no need for bit-addressability.  
R0 – R7 are not bit-addressable
PSW (Program Status Word), IP (Interrupt Priority Control), IE (Interrupt Enable Control), SCON (Serial Control), TCON (Timer Control)  

50. Figure A-2. 128 Bytes of Internal RAM
Byte address 7F
General purpose RAM 30
Bit-addressable locations 2F 7F 7E 7D 7C 7B 7A 79 78 77 76 75 74 73 72 71 70 6F 6E 6D 6C 6B 6A 69 68 67 66 65 64 63 62 61 60 5F 5E 5D 5C 5B 5A 59 58 57 56 55 54 53 52 51 50 4F 4E 4D 4C 4B 4A 49 48 47 46 45 44 43 42 41 40 3F 3E 3D 3C 3B 3A 39 38 37 36 35 34 33 32 31 30 2F 2E 2D 2C 2B 2A 29 28 27 26 25 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 15 14 13 12 11 10 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00 2E 2D 2C 2B 2A 29 28
Ask assembler 如何分辨 bit address 與 byte address. Ex: SETB 25H; MOV A, 25H; MOV C,25H. Answer: 由指令看出, 在訂定 instructions 時就決定了, 基本上有規則, 但仍會有奇怪的地方. 所以 appendix 中 instruction set 這些表格是很重要的. 27 26 25 24 23 22 21 20 1F
Bank 3 18 17
Bank 2 10 0F
Bank 1  08 07
Default register bank for R0 - R7 00

51. Access RAM MOV 30H, A E530 MOV R1, 30H A930 PUSH 07H C007
SETB 07H D207
PUSH R7 is wrong!

52. Figure A-1. SFR RAM Address (Byte and Bit) (1/2)
Special Function Registers
Byte address
Bit address
F7 F6 F5 F4 F3 F2 F1 F0
E7 E6 E5 E4 E3 E2 E1 E0
D7 D6 D5 D4 D3 D2 D1 D0
A7 A6 A5 A4 A3 A2 A1 A0
AF AC AB AA A9 A8
B7 B6 B5 B4 B3 B2 B1 B0
BC BB BA B9 B8 FF F0 E0 D0 B8 B0 A8 A0 B
ACC
PSW IP P3 IE P2

53. Figure A-1. SFR RAM Address (Byte and Bit) (2/2)
Special Function Registers
9F 9E 9D 9C 9B 9A
8F 8E 8D 8C 8B 8A
not bit addressable 99 98 90 8D 8C 8B 8A 89
SBUF
SCON
TH1
TL0 P1
TMOD
DPH 88 87 83 82 81 80
TH0
TL1
TCON
PCON
DPL SP P0 

54. Access SFRs Each SFR has a byte address.
Addresses from 80H to F0H
PUSH ACC C0E0
PUSH 0E0H C0E0
For a bit-addressable SFR, each pin of the register has a bit address.
SETB ACC D2E0
SETB 0E0H D2E0
SETB PSW D2D7

55. Bit Address of I/O Ports
Each port has its byte address.
Ex: P0 has byte address 80H.
Each pin of port has its bit address.
Ex: pin 7 of port 0 (P0.7) has bit address 87H
Figure A-1 SFR RAM address (p557)
Note that pin 0 of port 0 also has address 80H. Your instruction decides that the operand is bit or byte. 

56. Access I/O Ports PUSH P3 C0B0 or PUSH 0B0H C0B0 SETB P3.0 D2B0
CLR P C2B0
SETB 0B0H D2B0

57. Single-bit Operations
Instructions used for single-bit operations
These instructions given in Table 4-4 can be used for any bit. 
Some instructions that allow single-bit operations, but only along with the carry flag (CY).  (see Chapter 6)
Examples:
CLR PSW.7 D2 D7
CLR C D3 

58. Table 4-4: Single-Bit Instructions
Function
SETB
bit
Set the bit (bit = 1)
CLR
Clear the bit (bit = 0)
CPL
Complement the bit (bit = NOT bit) JB
bit,target
Jump to target if bit = 1 (jump if bit)
JNB
Jump to target if bit = 0 (jump if no bit)
JBC
Jump to target if bit = 1, clear bit (jump if bit, then clear)
These instructions can be used for any bit. 

59. Carry Bit-Related Instructions
Function
SETB C
make CY = 1
CLR C
clear carry bit (CY = 0)
CPL C
complement carry bit
MOV b,C
copy carry status to bit location (b = CY)
MOV C,b
copy bit location status to carry (CY = b)
JNC target
jump to target if CY = 0
JC target
jump to target if CY = 1
ANL C,bit
AND CY with bit and save it on CY
ANL C,/bit
AND CY with inverted bit and save it on CY
ORL C,bit
OR CY with bit and save it on CY
ORL C,/bit
OR CY with inverted bit and save it on CY

60. Reading a Single Bit into the Carry Flag
We use the carry flag to save or examine the status of a single bit of the port.
Use “MOV C,P2.1”
Then use the instructions to test and branch
JC target ; jump if carry (CY=1)
HERE: JC HERE ;jump to HERE if CY=1
JNC bit ; jump if not carry (CY=0)
HERE: JNC HERE ;jump to HERE if CY=0
See Examples 4-6 and 4-7 

61. Example 4-2 (a-1) Write the following program.
Create a square wave of 50% duty cycle on bit 0 of port 1.
Solution:
The 50% duty cycle means that the period of “on” state is 50% in the period of the whole pulse (“on” state pluses “off” state).
That is, the “on” and “off” state have the same length.
8051
P1.0
on state high portion
off state low portion
50%
50%
whole pulse

62. Example 4-2 (a-2)
Create a square wave of 50% duty cycle on bit 0 of port 1.
HERE:SETB P1.0 ;set to high bit 0 of port 1
LCALL DELAY ;call the delay subroutine
CLR P1.0 ;P1.0=0
LCALL DELAY
SJMP HERE
Another way to write the above program is:
HERE:CPL P1.0 ;complement bit 0 of port 1

63. Example 4-2 (b-1) Write the following programs.
(b) Create a square wave of 66% duty cycle on bit 3 of port 1.
Solution:
The 66% duty cycle means that the period of “on” state is 66% in the period of the whole pulse.
That is the “on” state is twice the “off” state.
8051
P1.3
66%
34%

64. Example 4-2 (b-2)
(b) Create a square wave of 66% duty cycle on bit 3 of port 1.
BACK:SETB P1.3 ;set port 1 bit 3 high
LCALL DELAY
CLR P1.3 ;clear bit 3 of port 1
SJMP BACK

65. Example 4-3 Write a program to perform the following.
(a) Keep monitoring the P1.2 bit until it becomes high,
(b) When P1.2 becomes high, write value 45H to port 0, and
(c) Send a high-to-low (H-to-L) pulse to P2.3.
Solution:
SETB P ;make P1.2 an input
MOV A,#45H ;A=45H
AGAIN:JNB P1.2,AGAIN;get out when P.2=1
MOV P0,A ;issue A to P0
SETB P ;make P2.3 high
CLR P ;make P2.3 low for H-to-L
Note：
1. JNB: jump if no bit（jump if P1.2 = 0 ）
2. a H-to-L pulse by the sequence of instructions SETB and CLR.
因為 P1.2 input pin 並不會在 JNB P1.2, Again 時被改掉, 仍為 1, 所以下次讀取時不用再設定一次.

66. Example 4-4
Assume that bit P2.3 is an input and represents the condition of an
oven. If it goes high, it means that the oven is hot.
Monitor the bit continuously.
Whenever it goes high, send a high-to-low pulse to port P1.5 to turn on a buzzer.
Solution:
SETB P ;make P2.3 an input
HERE:JNB P2.3,HERE ;keep monitoring for high
SETB P ;set bit P1.5=1
CLR P ;make high-to-low
SJMP HERE ;keep repeating

67. Example 4-5
A switch (SW) is connected to pin P1.7. Write a program to check the status of SW and perform the following:
(a) If SW=0, send letter ‘N’ to P2.
(a) If SW=1, send letter ‘Y’ to P2.
Solution:
SETB P ;make P1.7 an input
AGAIN: JB P1.7,OVER ;jump if P1.7=1
MOV P2,#’N’ ;SW=0, P2=‘N’
SJMP AGAIN ;keep monitoring
OVER: MOV P2,#’Y’ ;SW=1, P2=‘Y’

68. Example 4-6
A switch (SW) is connected to pin P1.7. Write a program to check the status of SW and perform the following:
(a) If SW=0, send letter ‘N’ to P2.
(a) If SW=1, send letter ‘Y’ to P2.
Solution:
SETB P ;make P1.7 an input
AGAIN: MOV C,P ;save P1.7 to carry
JC OVER ;jump if SW=1
MOV P2,#’N’ ;SW=0, P2=‘N’
SJMP AGAIN ;keep monitoring
OVER: MOV P2,#’Y’ ;SW=1, P2=‘Y’
Example 4-6 與 Example 4-5 相同, 只不過用到 MOV C, P1.7 及 JC OVER

69. Example 4-7
A switch is connected to pin P1.0 and an LED to pin P2.7. Write a program to get the status of SW and send it to the LED.
Solution:
SETB P ;make P1.0 an input
AGAIN: MOV C,P ;save P1.0 to carry
MOV P2.7,C ;send to LED
SJMP AGAIN ;keep repeating
Note：
“MOV P2.7, P1.0” is wrong since such an instruction does not exists. However, “MOV P2, P1” is a valid instruction.
MOV P2,P1 組譯後為 A0 (MOV source-data-addr, destination-data-addr) ,執行時仍是 MOV P2,P1.
但若是 MOV P0.3, P0.1 會無法組譯成功 illegal operand.
MOV C, P2.1 則是 valid.

70. You are able to List the 4 ports of the 8051
Describe the dual role of port 0 in providing both data and address
Code Assembly language to use the ports for input or output
Explain the use of port 3 for interrupt signals
Code 8051 instructions for I/O handling
Code bit-manipulation instructions in the 8051