Presentation is loading. Please wait.

Presentation is loading. Please wait.

Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 20alt1 Lecture 20alt DFT: Partial, Random-Access & Boundary Scan n Definition n Partial-scan architecture.

Published by Modified over 9 years ago

Similar presentations

Presentation on theme: "Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 20alt1 Lecture 20alt DFT: Partial, Random-Access & Boundary Scan n Definition n Partial-scan architecture."— Presentation transcript:

1 Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 20alt1 Lecture 20alt DFT: Partial, Random-Access & Boundary Scan n Definition n Partial-scan architecture n Historical background n Cyclic and acyclic structures n Partial-scan by cycle-breaking  S-graph and MFVS problem  Test generation and test statistics  Partial vs. full scan  Partial-scan flip-flop n Random-access scan (RAS) n Scan-hold flip-flop (SHFF) n Boundary scan IEEE 1149.1 standard n Summary

2 Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 20alt2 Partial-Scan Definition n A subset of flip-flops is scanned. n Objectives:  Minimize area overhead and scan sequence length, yet achieve required fault coverage  Exclude selected flip-flops from scan:  Improve performance  Allow limited scan design rule violations  Allow automation:  In scan flip-flop selection  In test generation  Shorter scan sequences

3 Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 20alt3 Partial-Scan Architecture FF SFF Combinational circuit PIPO CK1 CK2 SCANOUT SCANIN TC

4 Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 20alt4 History of Partial-Scan n Scan flip-flop selection from testability measures, Trischler et al., ITC-80; not too successful. n Use of combinational ATPG:  Agrawal et al., D&T, Apr. 88  Functional vectors for initial fault coverage  Scan flip-flops selected by ATPG  Gupta et al., IEEETC, Apr. 90  Balanced structure  Sometimes requires high scan percentage n Use of sequential ATPG:  Cheng and Agrawal, IEEETC, Apr. 90; Kunzmann and Wunderlich, JETTA, May 90  Create cycle-free structure for efficient ATPG

5 Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 20alt5 Difficulties in Seq. ATPG n Poor initializability. n Poor controllability/observability of state variables. n Gate count, number of flip-flops, and sequential depth do not explain the problem. n Cycles are mainly responsible for complexity. n An ATPG experiment: Circuit Number of Number of Sequential ATPG Fault gates flip-flops depth CPU s coverage TLC 355 21 14* 1,247 89.01% Chip A 1,112 39 14 269 98.80% * Maximum number of flip-flops on a PI to PO path

6 Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 20alt6 Benchmark Circuits Circuit PI PO FF Gates Structure Sequential depth Total faults Detected faults Potentially detected faults Untestable faults Abandoned faults Fault coverage (%) Fault efficiency (%) Max. sequence length Total test vectors Gentest CPU s (Sparc 2) s1196 14 18 529 Cycle-free 4 1242 1239 0 3 0 99.8 100.0 3 313 10 s1238 14 18 508 Cycle-free 4 1355 1283 0 72 0 94.7 100.0 3 308 15 s1488 8 19 6 653 Cyclic -- 1486 1384 2 26 76 93.1 94.8 24 525 19941 s1494 8 19 6 647 Cyclic -- 1506 1379 2 30 97 91.6 93.4 28 559 19183

7 Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 20alt7 Cycle-Free Example F1 F2 F3 Level = 1 2 F1 F2 F3 Level = 1 2 3 3 d seq = 3 s - graph Circuit All faults are testable. See Example 8.6.

8 Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 20alt8 Relevant Results n Theorem 8.1: A cycle-free circuit is always initializable. It is also initializable in the presence of any non-flip-flop fault. n Theorem 8.2: Any non-flip-flop fault in a cycle-free circuit can be detected by at most d seq + 1 vectors. n ATPG complexity: To determine that a fault is untestable in a cyclic circuit, an ATPG program using nine-valued logic may have to analyze 9 Nff time-frames, where Nff is the number of flip-flops in the circuit.

9 Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 20alt9 A Partial-Scan Method n Select a minimal set of flip-flops for scan to eliminate all cycles. n Alternatively, to keep the overhead low only long cycles may be eliminated. n In some circuits with a large number of self-loops, all cycles other than self-loops may be eliminated.

10 Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 20alt10 The MFVS Problem n For a directed graph find a set of vertices with smallest cardinality such that the deletion of this vertex-set makes the graph acyclic. n The minimum feedback vertex set (MFVS) problem is NP-complete; practical solutions use heuristics. n A secondary objective of minimizing the depth of acyclic graph is useful. 12 3 456 L=3 1 2 3 45 6 L=2 L=1 s-graph A 6-flip-flop circuit

11 Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 20alt11 Test Generation n Scan and non-scan flip-flops are controlled from separate clock PIs:  Normal mode – Both clocks active  Scan mode – Only scan clock active n Seq. ATPG model:  Scan flip-flops replaced by PI and PO  Seq. ATPG program used for test generation  Scan register test sequence, 001100…, of length n sff + 4 applied in the scan mode  Each ATPG vector is preceded by a scan-in sequence to set scan flip-flop states  A scan-out sequence is added at the end of each vector sequence n Test length = (n ATPG + 2) n sff + n ATPG + 4 clocks

12 Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 20alt12 Partial Scan Example n Circuit: TLC n 355 gates n 21 flip-flops Scan Max. cycle Depth* ATPG Fault sim. Fault ATPG Test seq. flip-flops length CPU s CPU s cov. vectors length 0 4 14 1,247 61 89.01% 805 805 4 2 10 157 11 95.90% 247 1,249 9 1 5 32 4 99.20% 136 1,382 10 1 3 13 4 100.00% 112 1,256 21 0 0 2 2 100.00% 52 1,190 * Cyclic paths ignored

13 Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 20alt13 Test Length Statistics n Circuit: TLC 200 100 0 0 50 100 150 200 250 Number of faults 200 100 0 0 5 10 15 20 25 Number of faults 200 100 0 0 5 10 15 20 25 Number of faults Without scan 9 scan flip-flops 10 scan flip-flops Test length Test length Test length

14 Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 20alt14 Partial vs. Full Scan: S5378 Original 2,781 179 0 0.0% 4,603 35/49 70.0% 70.9% 5,533 s 414 Full-scan 2,781 0 179 15.66% 4,603 214/228 99.1% 100.0% 5 s 585 105,662 Number of combinational gates Number of non-scan flip-flops (10 gates each) Number of scan flip-flops (14 gates each) Gate overhead Number of faults PI/PO for ATPG Fault coverage Fault efficiency CPU time on SUN Ultra II 200MHz processor Number of ATPG vectors Scan sequence length Partial-scan 2,781 149 30 2.63% 4,603 65/79 93.7% 99.5% 727 s 1,117 34,691

15 Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 20alt15 Flip-flop for Partial Scan n Normal scan flip-flop (SFF) with multiplexer of the LSSD flip-flop is used. n Scan flip-flops require a separate clock control:  Either use a separate clock pin  Or use an alternative design for a single clock pin Master latch Slave latch D SD TC CK MUX SFF (Scan flip-flop) Q TC CK Normal modeScan mode

16 Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 20alt16 Random-Access Scan (RAS) PO PI Combinational logic RAM n ff bits SCANOUT SCANIN CK TC ADDRESS ACK Address scan register log 2 n ff bits Address decoder SEL

17 Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 20alt17 RAS Flip-Flop (RAM Cell) Scan flip-flop (SFF) Q To comb. logic D SD From comb. logic SCANIN TC CK SEL SCANOUT

18 Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 20alt18 RAS Applications n Logic test:  Reduced test length  Reduced scan power n Delay test: Easy to generate single-input-change (SIC) delay tests. n Advantage: RAS may be suitable for certain architecture, e.g., where memory is implemented as a RAM block. n Disadvantages:  Not suitable for random logic architecture  High overhead – gates added to SFF, address decoder, address register, extra pins and routing

19 Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 20alt19 Scan-Hold Flip-Flop (SHFF) n The control input HOLD keeps the output steady at previous state of flip-flop. n Applications:  Reduce power dissipation during scan  Isolate asynchronous parts during scan test  Delay testing SFF D SD TC CK HOLD Q Q To SD of next SHFF

20 Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 20alt20 Boundary Scan (BS) IEEE 1149.1 Standard n Developed for testing chips on a printed circuit board (PCB). n A chip with BS can be accessed for test from the edge connector of PCB. n BS hardware added to chip:  Test Access port (TAP) added  Four test pins  A test controller FSM  A scan flip-flop added to each I/O pin. n Standard is also known as JTAG (Joint Test Action Group) standard. n Chapter 16

21 Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 20alt21 Boundary Scan Test Logic

22 Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 20alt22 Instruction Register Loading

23 Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 20alt23 System View of Interconnect

24 Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 20alt24 Elementary Boundary Scan Cell

25 Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 20alt25 Serial Boundary Scan Other implementations: 1. Parallel scan, 2. Multiple scans. Edge connector PCB or MCM

26 Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 20alt26 Summary n Partial-scan is a generalization of scan:  Scan can vary from 0 to 100%.  Elimination of long cycles can improve testability via sequential ATPG.  Elimination of all cycles and self-loops allows combinational ATPG.  Partial-scan has lower overheads (area and delay) and reduced test length.  Partial-scan allows limited violations of scan design rules, e.g., a flip-flop on a critical path may not be scanned. n Random Access Scan (RAS) reduces test time and power but has high overhead. n IEEE 1149.1 Boundary Scan standard is useful in system test.

Download ppt "Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 20alt1 Lecture 20alt DFT: Partial, Random-Access & Boundary Scan n Definition n Partial-scan architecture."

Similar presentations

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 23/19alt1 Lecture 23 Design for Testability (DFT): Full-Scan (Lecture 19alt in the Alternative Sequence)

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 23/19alt1 Lecture 23 Design for Testability (DFT): Full-Scan (Lecture 19alt in the Alternative Sequence)
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt1 Lecture 31 System Test (Lecture 22alt in the Alternative Sequence) n Definition n Functional.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 31/22alt1 Lecture 31 System Test (Lecture 22alt in the Alternative Sequence) n Definition n Functional.
Copyright 2001, Agrawal & BushnellLecture 12: DFT and Scan1 VLSI Testing Lecture 10: DFT and Scan n Definitions n Ad-hoc methods n Scan design  Design.

Copyright 2001, Agrawal & BushnellLecture 12: DFT and Scan1 VLSI Testing Lecture 10: DFT and Scan n Definitions n Ad-hoc methods n Scan design  Design.
Apr. 20, 2001VLSI Test: Bushnell-Agrawal/Lecture 311 Lecture 31 System Test n Definition n Functional test n Diagnostic test  Fault dictionary  Diagnostic.

Apr. 20, 2001VLSI Test: Bushnell-Agrawal/Lecture 311 Lecture 31 System Test n Definition n Functional test n Diagnostic test  Fault dictionary  Diagnostic.
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 261 Lecture 26 Logic BIST Architectures n Motivation n Built-in Logic Block Observer (BILBO) n Test.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 261 Lecture 26 Logic BIST Architectures n Motivation n Built-in Logic Block Observer (BILBO) n Test.
1 A Random Access Scan Architecture to Reduce Hardware Overhead Anand S. Mudlapur Vishwani D. Agrawal Adit D. Singh Department of Electrical and Computer.

1 A Random Access Scan Architecture to Reduce Hardware Overhead Anand S. Mudlapur Vishwani D. Agrawal Adit D. Singh Department of Electrical and Computer.
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 13/12alt1 Lecture 13 Sequential Circuit ATPG Time-Frame Expansion (Lecture 12alt in the Alternative.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 13/12alt1 Lecture 13 Sequential Circuit ATPG Time-Frame Expansion (Lecture 12alt in the Alternative.
1 Lecture 10 Sequential Circuit ATPG Time-Frame Expansion n Problem of sequential circuit ATPG n Time-frame expansion n Nine-valued logic n ATPG implementation.

1 Lecture 10 Sequential Circuit ATPG Time-Frame Expansion n Problem of sequential circuit ATPG n Time-frame expansion n Nine-valued logic n ATPG implementation.
Mar. 23, 2001VLSI Test: Bushnell-Agrawal/Lecture 201 Lecture 20 Delay Test n Delay test definition n Circuit delays and event propagation n Path-delay.

Mar. 23, 2001VLSI Test: Bushnell-Agrawal/Lecture 201 Lecture 20 Delay Test n Delay test definition n Circuit delays and event propagation n Path-delay.
1 Chapter Design For Testability. 2 6.5 The Scan-Path Technique The testing problems with sequential circuit can be overcome by two properties: 1.The.

1 Chapter Design For Testability The Scan-Path Technique The testing problems with sequential circuit can be overcome by two properties: 1.The.
Dec 21, Design for Testability Virendra Singh Indian Institute of Science Bangalore {computer, ieee}.org IEP on Digital System.

Dec 21, Design for Testability Virendra Singh Indian Institute of Science Bangalore {computer, ieee}.org IEP on Digital System.
FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR SRAM-based FPGA n SRAM-based LE –Registers in logic elements –LUT-based logic element.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR SRAM-based FPGA n SRAM-based LE –Registers in logic elements –LUT-based logic element.
Nov. 21, 2006ATS'06 1 Spectral RTL Test Generation for Gate-Level Stuck-at Faults Nitin Yogi and Vishwani D. Agrawal Auburn University, Department of ECE,

Nov. 21, 2006ATS'06 1 Spectral RTL Test Generation for Gate-Level Stuck-at Faults Nitin Yogi and Vishwani D. Agrawal Auburn University, Department of ECE,
Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 21alt1 Lecture 21alt BIST -- Built-In Self-Test (Alternative to Lectures 25, 26 and 27) n Definition.

Copyright 2005, Agrawal & BushnellVLSI Test: Lecture 21alt1 Lecture 21alt BIST -- Built-In Self-Test (Alternative to Lectures 25, 26 and 27) n Definition.
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 71 Lecture 7 Fault Simulation n Problem and motivation n Fault simulation algorithms n Serial n Parallel.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 71 Lecture 7 Fault Simulation n Problem and motivation n Fault simulation algorithms n Serial n Parallel.
Lecture 20 Delay Test (Lecture 17alt in the Alternative Sequence)

Lecture 20 Delay Test (Lecture 17alt in the Alternative Sequence)
Copyright 2001, Agrawal & BushnellDay-2 PM Lecture 101 Design for Testability Theory and Practice Lecture 10: DFT and Scan n Definitions n Ad-hoc methods.

Copyright 2001, Agrawal & BushnellDay-2 PM Lecture 101 Design for Testability Theory and Practice Lecture 10: DFT and Scan n Definitions n Ad-hoc methods.
1 Lecture 20 Delay Test n Delay test definition n Circuit delays and event propagation n Path-delay tests  Non-robust test  Robust test  Five-valued.

1 Lecture 20 Delay Test n Delay test definition n Circuit delays and event propagation n Path-delay tests  Non-robust test  Robust test  Five-valued.
Nitin Yogi and Vishwani D. Agrawal Auburn University Auburn, AL 36849

Nitin Yogi and Vishwani D. Agrawal Auburn University Auburn, AL 36849
1 Lecture 23 Design for Testability (DFT): Full-Scan n Definition n Ad-hoc methods n Scan design Design rules Scan register Scan flip-flops Scan test sequences.

1 Lecture 23 Design for Testability (DFT): Full-Scan n Definition n Ad-hoc methods n Scan design Design rules Scan register Scan flip-flops Scan test sequences.

Similar presentations

Ads by Google