1. CMPE222 Project Synthesis Optimization ------ analysis of DC & DW Zhenrong Wang, Mingcui Zhou @EE Instructor: Prof. Wakefield

2. 2 Outline Preparation for Synthesis: source code HDL level Optimization Optimization using Design_analyzer constraints & DesignWare Depth study of Synthesis Optimization ----look into DesignWare * Build your own synthesis Library (Optional)

3. 3 (I) HDL Level Optimization Using FIR 3 Tap 3 latency version: combine status (wait, load) and (shift, output) Simulator: Modelsim 5.5 SEb

4. 4 Output verification 2 latency version : wait and combine all the calcuation states into one

5. 5 HDL level Optimization Compare compiling results: PowerAreaDelayTotal 2latency6.96768802429.65.367 3latency9.89287788259.617.493

6. 6 Reason for difference Less status for less Power More combined calculation hinder reuse of adders and multipliers

7. 7 Conclusion for HDL Optimization Conciseness may not be the best but it’s good approach!

8. 8 (II) Adding Constraints

9. 9 Wishing for the best result? If constraints ( Max area == 0 && Max delay == 0 && Power ==0 ) Compiling time = hours long; Result = WORSE;

10. 10 Understand how it works

11. 11 Foundation Library Design Library (.syn, etc) contains the circuit descriptions that are immediately usable by the Synopsys tools. Synthetic Library (.sldb) links the circuits in a design library to the Synopsys Synthesis tools /projects/cadlab/synopsys/2001.08/dw /dw0*/lib  Design library /projects/cadalb/synopsys/2001.08 /libraries/syn  Synthetic Library

12. 12 Default Synthesis Library standard.sldb List name of default: “Synthetic Operator” “Synthetic Model” “Implementations” “binding relationship of each level”

13. 13 Synthetic Library Structure

14. 14 The standard.sldb of synopsys See what contains in the synopsys default synthesis library (different to users with different license) > cd /projects/cadlab/synopsys/2001.08 /library/syn/ >Source your_synopsys.rc >dc_shell //enter dc_shell dc_shell> report_synlib standard.sldb

15. 15 Contents of.sldb Synthetic operator type ADD_TC_CI_OP add ADD_TC_OP add Synthetic model desciprtion DW01_add design_library: DW01 HDL parameter: width =... Synthetic model Implimentation DW02_mult sim v csa leg = "(A_width>=1) &

16. 16 Examples of tracing component

17. 17 Bounding of each level Synthetic Model DW02_mult … b2 bound_operator: MULT_UNS_OP Pin Associations (module, oper): A, A B, B … … --------------------------------------------------------------------------- Module Implementations Attributes/Parameters -------------------------------------------------------------------------- DW02_mult sim v csa leg = "(A_width>=1) &&…

18. How constraints works?

19. 19 Implementation Selection

20. 20 How to optimize To characterize the implementations for comparison, the synthesis tool creates a pre-optimized model for each one, in the user’s target technology. The timing and area characteristics of the models serve as the basis for implementation selection.

21. 21 Content of technology.db Main parts Area time cell(OR2I) { area : 2; cell_footprint : "or2"; pin(A) { direction : input; capacitance : 1; } … … { intrinsic_rise : 0.18; intrinsic_fall : 0.65; rise_resistance : 0.223; fall_resistance : 0.0083;

22. What if we choose both: max area==0&&delay==0

23. Tools optimize timing first by default!

24. 24 One constraint Each time(1) 2-latency version Typical db Dynamic Power Cell AreaArrival Time Total Default6.9676802429.65.367 Area7.0365807089.615.457 Timing7.603864399.616.315 Fanout6.9093783339.65.195

25. 25 One constraint each time (2) 3-latency version Typical db Dynamic Power Cell AreaArrival Time Total Default9.8928788259.617.493 Area9.4758734539.616.688 Timing9.4939774219.567.268 Fanout9.4045775489.627.015

26. 26 Tips Area constraint has the more impact on the optimization compared to others High-level behavioral optimization reduces the area, power a lot. Fanout constraint reduce the timing but increase the dynamic power Default optimization is, in common case, good enough for timing optimization

27. 27 III DesignWare Best case for non-DW & DW Dynamic Power Cell Area Arrival Time Total DW6.78609339.63.966 Non-DW9.4758734539.616.688

28. 28 Advantages of using DW It offers many different design descriptions (implementations) for a given function; users let the synthesis tools choose which implementation to use in any given context.

29. 29 See datasheet of DW

30. 30 Check information in datasheet symbols Ports description Parameter Implimentations …

31. 31 Setup environment for DW you must set two dc_shell variables: synthetic_library and link_library. Add in.synopsys_dc.setup “ … synthetic_library = dw01.sldb dw02.sldb; link_library = { typical.db dw01.sldb dw02…}

32. 32 How are DesignWare Foundation Components Used? Component instantiation: Operator Inferencing

33. 33 Instantiate Example // Instantiating DW02_multp in Verilog module adder(a, b, tc, out); parameter wordlength = 24; input [wordlength- 1:0] a, b; … // instantiate DW01_add DW02_multp #(wordlength) U1(a,b,tc,out); endmodule

34. 34 example

35. 35 Results after Instantiating Using DW_multp/wall DesignWare db (3 latency) Dynamic Power Cell AreaArrival time Total Default2.9248548829.581.537 Area2.9062497299.551.38 Timing2.9274543539.421.498 Fanout2.9319552089.501.537

36. 36 Set model/implementation always @(in1 or in2) begin :b1 /* synopsys resource r0: map_to_module = ”DW01_add”, implementation = ”cla”, ops = ”a1”; */ sum <= in1 + in2; //synopsys label a1

37. 37 Disabling Selected Synthetic Modules and Implementations Tools use the first one if there’s models with same names Disable using models in synthetic lib: set_dont_use standard.sldb/DW01_addsub

38. 38 Developing Synthetic Library