1. 1 Scalable E-mode N-polar GaN MISFET devices and process with self-aligned source/drain regrowth Uttam Singisetti*, Man Hoi Wong, Sansaptak Dasgupta, Nidhi, Brian Swenson, Brian Thibeault, Jim Speck, and Umesh Mishra ECE and Materials Departments University of California, Santa Barbara, CA 2010 Device Research Conference University of Notre Dame, South Bend, IN * uttam@ece.ucsb.edu

2. 2 Outline Motivation – Why E-mode, N-polar Device design and Process – Self-aligned device process – E-mode device design Results – Optical gate devices DC and RF data Conclusion and Future work

3. 3 Why E-mode GaN devices GaN devices  high speed and high breakdown  high Johnston figure of merit D-mode HEMTs with f t ~ 200 GHz, f max ~ 300 GHz Motivation for E-mode −Single voltage supply circuit −Simplified circuits −E-mode/D-mode logic circuits Figure source:. T. Palacios group, MIT

4. 4 Ga-face GaN buffer Al(Ga)N 2DEG N-face Barrier GaN Al(Ga)N 2DEG GaN buffer +++++++++++ Si doping − Back barrier for electron confinement  higher g m − No higher bandgap AlGaN layer on top  low resistance contacts Scaling advantages of N-polar GaN Why E-mode, why N-polar GaN N-face AlGaN GaN EFEF ECEC VPVP

5. 5 Ga-polar E-mode devices with alloyed contacts Source/drain contacts to highband gap AlGaN layers  parasitic source contact resistance  high R on, g m degradation, scaling issues Higashiwaki, IEEE TED 2006 K.Chen, IEEE TED 2006 Thinning down barrier under the gate Thicker barrier in the access regions F - on incorporation under the gate Thicker barrier in the access regions

6. 6 Self-aligned scaled E-mode devices − Self-aligned InGaN grade/InN source/drain to reduce access resistance* − Sub 100 nm gate-lengths  velocity overshoot − Vertical scaling of channel to keep high aspect ratio Ultra scaled GaN devices: f t, f max > 200 GHz Figure source:. T. Palacios group, MIT * S.Dasgupta, APL 2010. Nidhi, IEDM 2009

7. 7 Device structure and design Under sidewall AlN removed under sidewall Under gate 20 nm channel Top AlN depletes 2-DEG under gate Under S/D contacts* * S.Dasgupta, APL 2010. Nidhi, IEDM 2009

8. 8 Device structure and design 20 nm GaN channel with AlN back barrier Depletion of 2-DEG under the gate by the top AlN, 5nm SiN x barrier Low R on achieved by Removing AlN from the access region to induce 2- DEG Regrowing n+ regions low contact resistance 4.5×10 12 cm -2 sheet electron density under the sidewall, indium-dot Hall measurement gives R sh ~ 1000 W/□, (n s = 4.5×10 12 cm -2, m = 1000 cm 2 /V.s) Under gate Under sidewall

9. 9 Device fabrication process * * U.Singisetti, pss(c) 2009, EDL 2009.

10. 10 Selective AlN etch on GaN channel − Digital etch 5 m UV ozone oxidation, BHF etch − 2 nm AlN etched in 4 cycles of etching − XPS on process monitor shows removal of AlN − Hall measurement gives n s = 3x10 12 cm -2, agrees well to simulation Band diagram after AlN etching ∫ n(x) dx = 3×10 12 cm -2 No Al signal after etching XPS of process monitor sample

11. 11 DC characteristics of E-mode devices I max = 0.2 A/mm for L g = 10  m device I max = 0.6 A/mm for L g = 1  m device

12. 12 DC characteristics of E-mode devices I max = 0.7 A/mm −V th = 0.8 V at V ds = 4.0V − I max = 0.7 A/mm, g m = 250 mS/mm at V ds = 4.0 V −I max = 0.22 A/mm, peak g m = 125 mS/mm at V ds = 0.5 V V th

13. 13 Low gate leakage Maximum gate leakage current of 7 mA/mm at V gs =5 V, and V ds =4.0 V

14. 14 0.23  m gate length device Device no longer E-mode at L g = 0.23 mm I max = 0.9 A/mm, peak g m = 210 mS/mm at V ds = 4.0 V

15. 15 Short channel effect Threshold voltage decreases with drain bias (V ds )

16. 16 Short channel effect V th roll off with gate length Device becomes D-mode at L g = 0.23  m because of low aspect ratio (L g /t = 230 nm/ 27 nm = 8.5) Short channel effect is because of low aspect ratio and self-aligned access regions Need more vertical scaling for sub-100 nm E-mode devices

17. 17 Device access resistance Source access resistance of 1  -mm, regrowth R sh = 1000  /□, R c = 0.2  -mm, high compared to D-mode devices* Reasons: Unintentional grading to In 0.3 Ga 0.7 N instead of In 0.6 Ga 0.4 N  Higher sheet resistance No InN coverage due to uncalibrated growth temperature  Higher R c R s can be easily reduced No InN R s + R d = 2  mm * S.Dasgupta, APL 2010. Nidhi, IEDM 2009

18. 18 Small-signal characteristics

19. 19 Conclusions and future work – Scalable self-aligned N-polar E-mode devices – V th = 0.8 V for L g = 0.55  m device – High current drive > 0.7 A/mm – Peak g m = 250 mS/mm – Short channel effects observed – Vertical scaling and gate length scaling – Optimized regrowth Future work