1. Analog-to-Digital Converters Lecture L11.2 Section 11.3

2. Analog-to-Digital Converters Converts analog signals to digital signals –8-bit: 0 – 255 –10-bit: 0 – 1023 –12-bit: 0 – 4095 Successive Approximation Flash

3. Method of Successive Approximation

4. Implementing Successive Approximation

5. ADC0831 8-Bit Serial I/O A/D Converter

8. Flash A/D Converter Uses analog comparators to convert an analog signal to a digital signal in a single clock cycle n-bit converter requires 2 n – 1 comparators –4-bit converter requires 15 comparators –8-bit converter requires 255 comparators Or two 4-bit converters plus a D/A converter

9. MAX118

10. Flash A/D Converter

11. MAX118

13. ADC0831 Timing

14. Voltmeter Logic Block Diagram

17. Q6 & Q7 (CS) Q3 Q4 Q5 Q6 Q7 Q3 (CLK) Data Out (DO) 7 6 5 4 3 2 1 0 !Q3 shift (S) 7 6 5 4 3 2 1 0 [Q7..Q4] == 10 (Capture) !Q3 display (D)

18. Q1 Q0 1.0 MHz Q20.5 MHz Q30.25 MHz 2.0 MHz Clock4.0 MHz

19. Q3 CLK Q7 Q6 CS DO Xilinx XC95108 PC84 CPLD Clock Divider Counter Q7..Q0 4 MHz Clock ADC0831 Interface

20. !Q3 display (D) [Q7..Q4] == 10 (Capture) Q6 & Q7 (CS) Q3 Q4 Q5 Q6 Q7 Q3 (CLK) Data Out (DO) 7 6 5 4 3 2 1 0 !Q3 shift (S) 7 6 5 4 3 2 1 0

21. Count Detect Logic (Q7..Q4 = 1010 2 ) Capture Xilinx XC95108 PC84 CPLD Clock Divider Counter Q7..Q0 4 MHz Clock Q3 Q7 Q6 CLK CS DO ADC0831 Interface Display Register D7..D0 ClockLoad Shift Register S7..S0 Clock Data Q3!Q3

22. 0 Binary-to-BCD Converter Hundreds Tens Units 0 7-Segment Decoder 7-Segment Decoder 77 Voltage Display a..g Xilinx XC95108 PC84 CPLD Display Register D7..D0 ClockLoad (Shift Register S7..S0) (Capture) (!Q3) dpt 1