1. 04/25/2006 ELEC 7250 Final Project: Jie Qin 1 Logic Simulator for Combinational Circuit Jie Qin Dept. of Electrical and Computer Engineering Auburn University, AL 36849, USA

2. 04/25/2006ELEC 7250: Jie Qin2 Problem Statement ► Develop a logic simulator with support for the standard bench format and the hierarchical bench format. ► When the output of the simulated circuit does not match the expected response, try to diagnose the error in the circuit using the logic simulator.

3. 04/25/2006ELEC 7250: Jie Qin3 Logic Simulator ► The implemented logic simulator consists of a compiler and a simulator. -- the compiler reads in a circuit description in bench format and builds a simulation table in memory. -- the compiler reads in a circuit description in bench format and builds a simulation table in memory. -- the simulator propagates the values provided from outside at the PIs to the POs utilizing the simulation table (logic propagation). -- the simulator propagates the values provided from outside at the PIs to the POs utilizing the simulation table (logic propagation).

4. 04/25/2006ELEC 7250: Jie Qin4 Simulation Table ► A simulation table is actually a list of gate records. All the PIs, gates and POs in a circuit are represented by the gate records in the implemented logic simulator. A gate record includes the following information. ID Name Class Fanin list (FIL) Fanout list (FOL) Fanin ’ s value (FIV) Gate ’ s value (GV)

5. 04/25/2006ELEC 7250: Jie Qin5 An Example of Simulation Table gate “ d ” gate “ e ” PI “ a ” PO “ f ” ID: 4 Name: f Class: PO FIL: {e} FOL: {f} FIV: {-1} GV: {-1} ID: 1 Name: d Class: AND FIL: {a, a} FOL: {e} FIV: {-1, -1} GV: {-1} a de f ID: 3 Name: a Class: PI FIL: {a} FOL: {d} FIV: {-1} GV: {-1} ID: 2 Name: e Class: NOT FIL: {d} FOL: {f} FIV: {-1} GV: {-1} before logic propagation before logic propagation

6. 04/25/2006ELEC 7250: Jie Qin6 Logic Propagation ► To propagate the known value at the PIs to the POs, two lists are maintained in the memory. -- passive list: it includes all the “ gate records ” whose outputs are in unknown states. -- passive list: it includes all the “ gate records ” whose outputs are in unknown states. -- active list: once a gate has its output in known state, it will be append to this list. However, after all the fanouts of this gate are determined as a known value, it will be removed from this list. -- active list: once a gate has its output in known state, it will be append to this list. However, after all the fanouts of this gate are determined as a known value, it will be removed from this list.

7. 04/25/2006ELEC 7250: Jie Qin7 An Example of Logic Propagation a b g f h Half-Adder c d e 0 1 0 1 0 1 1 active list passive list a b hg e dc f 1 0 0 1 1 0 1 1

8. 04/25/2006ELEC 7250: Jie Qin8 Results for a 4-bit Ripple Adder

9. 04/25/2006ELEC 7250: Jie Qin9 Results for ISCAS ’ 85 Circuits

10. 04/25/2006ELEC 7250: Jie Qin10 Fault Diagnosis ► Assumption #1: the internal state of the CUT cannot observed from the outside ► Assumption #2: the possibility of single fault is much higher than multiple faults ► Approach: -- Step #1: for each faulty PO, obtain a reversed logic cone from PO; -- Step #1: for each faulty PO, obtain a reversed logic cone from PO; -- Step #2: intersect the logic cones obtained in Step #1; -- Step #2: intersect the logic cones obtained in Step #1; -- Step #3: try more test vectors to obtain a logic cone as small as possible. -- Step #3: try more test vectors to obtain a logic cone as small as possible.

11. 04/25/2006ELEC 7250: Jie Qin11 Conclusion ► The execution time increases with the number of gates and the number of test vectors. ► The fault diagnosis still needs to be improved because the assumption does not match the real situation very well.

12. 04/25/2006ELEC 7250: Jie Qin12 Thank you !