1. March 2005 1R. Smith - University of St Thomas - Minnesota ENGR 330: Today’s Class Homework 8 recap; Homework 9 questionsHomework 8 recap; Homework 9 questions Virtual MemoryVirtual Memory Page faultsPage faults Pentium address structurePentium address structure

2. March 2005 2R. Smith - University of St Thomas - Minnesota HW 8: Pipelined instruction features Same lengthSame length –Obviously true Consistent Instruction layoutConsistent Instruction layout –Registers always in same fields for same purposes –4 bits for opcode –3 bits for the destination register specification –3 bits for a base or source register –3 bits used for immediate operands –3 bits of either source register #2 or immediate operand Memory references limited to loads and storesMemory references limited to loads and stores –Are Jump instructions memory reference instructions? Operands are aligned in RAMOperands are aligned in RAM –Everything is done in terms of 16-bit words –Misalignment can only happen in byte-oriented machines

3. March 2005 3R. Smith - University of St Thomas - Minnesota HW 8: Pipelining Diagrams What is a data path?What is a data path? –Highlighting the wires was enough. Highlighting registers/ALUs not. Step 1Step 1 –You have to increment the PC Step 2Step 2 –You need both registers and sign extend –Upper PC line is harmless but unnecessary Step 3Step 3 –Register 1 + offset yields the address –Register 2 passes through to RAM Write Step 4Step 4 –ALU result to RAM address; Register 2 to RAM Write There is NO Step 5 in a Store instruction!There is NO Step 5 in a Store instruction!

4. March 2005 4R. Smith - University of St Thomas - Minnesota The “SW” Instruction Need ‘wire’ highlighting, tooNeed ‘wire’ highlighting, too

5. March 2005 5R. Smith - University of St Thomas - Minnesota Questions on homework 9 Cache hits in a 16-word direct mapped cacheCache hits in a 16-word direct mapped cache –Cache mapping is modulo-16 Other questions?Other questions?

6. March 2005 6R. Smith - University of St Thomas - Minnesota Elements of Paging Virtual address sizeVirtual address size –What the program/CPU sees Real address sizeReal address size –What the RAM really contains (MAR width) Page sizePage size Page Table SizePage Table Size –One entry for each page in virtual address space –Smaller if we use a “directory” scheme Page Table Entry sizePage Table Entry size –Large enough to count all pages in RAM –Extra “control” bits: valid, protected, used, dirty “Directory Levels”“Directory Levels” –A way to build page tables in chunks –Doesn’t need one huge table to handle a huge address space

7. March 2005 7R. Smith - University of St Thomas - Minnesota Virtual Memory The overview: RAM as cacheThe overview: RAM as cache Mapping a regular pageMapping a regular page Handling a page faultHandling a page fault

8. March 2005 8R. Smith - University of St Thomas - Minnesota Virtual address resolution CPU refers to a virtual address (loads its MAR)CPU refers to a virtual address (loads its MAR) Translation Lookaside Buffer tries itTranslation Lookaside Buffer tries it Index into the page tableIndex into the page table –If table entry is valid, Append page address to offsetAppend page address to offset DoneDone –Else Block the process; read the pageBlock the process; read the page

9. March 2005 9R. Smith - University of St Thomas - Minnesota Reading in a missing page Find a page in RAM we can useFind a page in RAM we can use –Look for “freed” pages –If none, pick one to “page out” If the “out” page is dirty, write it to HDIf the “out” page is dirty, write it to HD Find the page on the HDFind the page on the HD Start an I/O operation to read it to RAMStart an I/O operation to read it to RAM When in RAM, update the PTEWhen in RAM, update the PTE Restart the instruction that caused the page faultRestart the instruction that caused the page fault

10. March 2005 10R. Smith - University of St Thomas - Minnesota Page directories A 4GB page table? No way!A 4GB page table? No way! –Well, maybe not for another few years anyway Page directoriesPage directories –Add a level of hierarchy to page tables –Directory is indexed like a page table –Its entry points to a page table for that part of the address –Lets us put practical limits on page table sizes –Allows gigantic RAM areas, physical and virtual –Allows “pageable” page tables

11. March 2005 11R. Smith - University of St Thomas - Minnesota Intel Virtual Address Formats “Control Register 3” (CR3)“Control Register 3” (CR3) –Processor special register –Points to the topmost page table directory for a process Standard x86 page tablesStandard x86 page tables –Bits 31-22: Page directory Index –Bits 21-12: Page table index –Bits 11-0: page offset Physical Address Extension (PAE)Physical Address Extension (PAE) –Bits 31-30: Page directory pointer index –Bits 29-20: Page directory index –Bits 19-12: Page table index –Bits 11-0: page offset

12. March 2005 12R. Smith - University of St Thomas - Minnesota IA-64 Virtual Addresses “Only” supports 48 bits right now“Only” supports 48 bits right now –250 trillion bytes? Enough for now? Address FormatAddress Format –Bits 47-39: Page map level 4 selector –Bits 38-30: Page directory pointer selector –Bits 29-21: Page table selector –Bits 20-12: Page table index –Bits 11-0: page offset

13. March 2005 13R. Smith - University of St Thomas - Minnesota Problems to work Working out addresses with page directoriesWorking out addresses with page directories Working out more page table problemsWorking out more page table problems

14. March 2005 14R. Smith - University of St Thomas - Minnesota That’s it. Questions?Questions? Creative Commons License This work is licensed under the Creative Commons Attribution-Share Alike 3.0 United States License. To view a copy of this license, visit http://creativecommons.org/licenses/by-sa/3.0/us/ or send a letter to Creative Commons, 171 Second Street, Suite 300, San Francisco, California, 94105, USA.