1. Performed by:Roi Sherman Eyal Wilamowski Instructor: Mr. Michael Itzkovich המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering דו ” ח סיכום פרויקט Subject: Generic Daughter Board For 5510 EVM סמסטר חורף \ אביב תשס " ב

2. Department of Electrical Engineering High Speed Digital Systems Laboratory 2 The project aim is to implement a general purpose daughter board for the TI 5510 EVM prototype board. The card could be used for connecting of up to 4 DSP’s through the McBSP for Parallel Computation and system resources sharing. The card would have the ability to operate as master in a standalone mode, or even connect to an expansion board of it’s own. The implemented card is generic as possible yielding maximum use of pins, connectors etc. High percent of all resources are not purpose and controlled by the main control unit. Abstract

3. Department of Electrical Engineering High Speed Digital Systems Laboratory 3 System Description The card developed is an expansion to the EVM 5510 Prototype Board. It contains an asynchronous SRAM memory, a Flash storage memory, serial communication channels. It also contains a GPIO signals that could be used to create an additional bus to the daughter boards’ FPGA. It has a memory, McBSP and general purpose interface to the DSP board. The onboard features includes in addition DC converter, Led indicators and power protections.

4. Department of Electrical Engineering High Speed Digital Systems Laboratory 4 Specification  Hardware:  Altera EPF10K100ARC-1 FPGA.  AMD Flash Memory AM29LV400BT-70.  Alliance Asynchronous SRAM AS7C34098-10TC.  TI TL16C550CPT Single UART.  Maxim MAX3238 RS-232 Transceivers.  Bus Transceivers SN74LVTH16245.  National’s LM1085 Voltage Regulator.  Software:  HW Verification SW in TIs’ Code Composer Studio environment.

5. Department of Electrical Engineering High Speed Digital Systems Laboratory 5 Control Unit (Altera) RS232 GPIO 2MB SRAM 1MB Flash MB Interface Peripheral Interface EMIF McBSP System Block Diagram

6. Department of Electrical Engineering High Speed Digital Systems Laboratory 6 Indicators Interface Memory Interface Spare MB Signals Interface UART Interface addr data ctrl data ctrl addr GPIO Interface ctrl Main Control FPGA Block Diagram