1. Leakage Components and Their Measurement
Puneet Sharma
ECE Department, UCSD
Goodmorning everybody. My name is Puneet Sharma. I am a fourth year Ph.D. student working under the supervision of Prof. Andrew Kahng. The title of my talk today is Manufacturing-Aware Physical Design Techniques.
UCSD VLSICAD Lab

2. Leakage Components Subthreshold leakage Gate direct tunneling leakage
Junction tunneling current (including gate induced drain leakage (GIDL) and band-to-band tunneling)
Others:
Hot carrier injection current
Punchthrough current
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3. Subthreshold Leakage (Isub)
Most significant component upwards of 25oC
Dominates gate direct tunneling until 65nm
High-K at 45nm and beyond will reduce gate direct tunneling
Occurs in “off” state (VGS < VTh) between source and drain
Two stacked devices (i.e., off devices in series) will dramatically reduce Isub for both (leakage current is the same for all devices in the stack but leakage power is primarily in the devices for which VS ≠ 0 (body effect))
Increases exponentially as VTh decreases
Increases exponentially with temperature
Depending on VTH roll-off curve, Isub can increase or decrease with LGate. For most processes Isub will increase significantly as LGate is reduced from nominal
SPICE Measurement
For NMOS
D=1, G=0, S=0, B=0
Measure b/w D and S
For PMOS
D=0, G=1, S=1, B=1
Isub
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4. Gate Direct Tunneling Leakage (IGate)
SPICE Measurement
For NMOS
IGCS D=0, G=1, S=0, B=0
Measure b/w G & S
IGCD D=0, G=1, S=0, B=0
Measure b/w G & D
IGSO D=X, G=0, S=1, B=0
IGDO D=1, G=0, S=X, B=0
Measure b/w G and D
IGB D=1, G=1, S=1, B=0
Measure b/w G and B
For PMOS
IGCS D=1, G=0, S=1, B=1
IGCD D=1, G=0, S=1, G=1
IGSO D=X, G=1, S=0, B=1
Measure b/w G and S
IGDO D=0, G=1, S=X, B=1
IGB D=0, G=0, S=0, B=1
In SPICE models IGCMOD must be 1 for IGC and IGBOD 1 for IGB
Due to quantum tunneling of electrons/holes through gate oxide
Increases as gate oxide thickness decreases and potential difference across gate oxide increases
Components:
Gate to channel (IGC)
Main contributor for NMOS
Occurs in “on” state and when source and drain are in opposite state from gate
Comprises of gate to source (IGCS) and gate to drain (IGCD)
Gate to source/drain overlap regions (a.k.a. edge direct tunneling (EDT))
Occurs in “off” state and when source and/or drain are in opposite state from gate
Comprise of gate to source (IGSO) and gate to drain (IGDO)
Gate to body (IGB)
Occurs in “on” state and source and drain are in same state as gate
Negligible for NMOS
Comparable to or larger than IGC for PMOS
Practically unaffected by threshold voltage and temperature
Isub
Channel in
“on” state
IGCS
IGCD
IGB
IGSO
IGDO
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5. Junction Tunneling Current
Occurs between drain/source to substrate due to band-to-band tunneling (BTBT) in “on” state and due to GIDL in “off” state
Occurs due to potential difference between body and source/drain  much more common to have drain-to-body leakage than source-to-body
GIDL occurs from drain to body when D=1, G=0, S=X, B=0
SPICE Measurement
For NMOS
IDB D=1, G=0, S=X, B=0
D=1, G=1, S=1, B=0
Measure b/w D and B
ISB D=1, G=1, S=1, B=0
Measure b/w S and B
For PMOS
IDB D=0, G=1, S=X, B=1
D=0, G=0, S=0, B=1
ISB D=0, G=0, S=0, B=1
ISB
IDB
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6. Other Leakage Components
Hot carrier injection
Generally not considered leakage but more of a reliability issue
Occurs from gate to substrate, increases as LGate is reduced
Over time, HCI causes VTh shift which changes Isub
Punchthrough current
Occurs from drain to source
Of concern only when physical gate length under 10nm
UCSD VLSICAD Lab

7. Reverse Short Channel Effect
Reverse short channel effect arises due to halo implants
Due to DIBL, short channel effect causes VTh to increase as LGate increases
To combat DIBL, halo implant is used for non-uniform doping (higher doping at S/D terminals, lower at channel center)
Halo induces reverse SCE (VTh decreases as LGate increases)
Affects subthreshold leakage only
Halo doping (pocket implant) profile
SCE
RSCE
[YuNNH96]
[YuNNH96]
UCSD VLSICAD Lab

8. Narrow Channel (Width) Effects
Narrow channel effects cause a shift in threshold voltage as channel width is reduced
depend primarily on isolation technique (LOCOS or STI)
For STI, reverse narrow channel effect (RNCE) is observed which cause VTh to decrease as width is decreased
For LOCOS, narrow channel effect (NCE) is observed which causes VTh to increase as width decreased
Reverse Narrow Channel Effect
[HsuehSDA88]
UCSD VLSICAD Lab

9. General Rules of Thumb
Every 3A change in Tox gives ~10X change in IGate. High-K will, however, will reduce IGate by 100x.
Subthreshold swing is usually ~85mV/dec at room temp. and a bit higher at operating temp (i.e., mV shift in VTh (or Vgs in subthreshold) will lead to 10X change in Isub.)
In most 65nm technologies, we found SCE to dominate RSCE up to 10% biasing
Gate biasing increases gate tunneling leakage due to increase in tunneling area. However, not enough to mitigate subthreshold leakage reductions over 250C
RNCE becomes noticeable under 300nm for 90nm process
Some results from AgarwalKMR04 (may not be general):
Variation of different leakage components with (a) oxide thickness, (b) doping profile. “Doping1” has a stronger halo profile than “Doping2”. For NMOS device 25nm and 50nm of effective channel length. [AgarwalKMR04]
Simulation result for variation of different leakage components with temperature for NMOS device (Leff=25nm) [AgarwalKMR04]
UCSD VLSICAD Lab

10. Sample Scripts and Results
All leakage components described in these slides (except for IGSO which is uncommon) can be mesured through the following three SPICE files in ~projects/LEAKAGE-TUT/example_scripts/
d1g0s0b0.sp (NMOS terminals set as d=1, g=0, s=0, b=0)
d0g1s0b0.sp
d1g1s1b0.sp
Results for NMOS, 90nm TT process, 1.2V, 80oC
Isub = 131.5pA
IDB (with GIDL) = 1.240pA
IDB = 1.202pA
ISB = 1.202pA
IGCD = pA
IGCS = pA
IGDO = pA
IGB = 2.277e-06pA
UCSD VLSICAD Lab

11. References
K. Roy, S. Mukhopadhyay, H. Mahmoodi-Meimand, “Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits”, IEEE 2003.
A. Keshavarzi, K. Roy and C. F. Hawkins, “Intrinsic Leakage in Low Power Deep Submicron CMOS ICs”, ITC 1997.
A. Agarwal, C. H. Kim, S. Mukhopadhyay and K. Roy, “Leakage in Nano-Scale Technologies: Mechanisms, Impact and Design Considerations”, DAC 2004.
D. J. Frank, “Power-Constrained CMOS Scaling Limits”, Vol. 46, No. 2/3, IBM Journal of R&D, 2002.
B. Yu, E. Nowak, K. Noda and C. Hu, “Reverse Short-Channel Effects & Channel-Engineering in Deep-Submicron MOSFET’s: Modeling and Optimization”, 1996.
K. Hsueh, J. Sanchez, T. Demassa and L. Akers, Inverse-Narrow-Width Effects and Small-Geometry MOSFET Threshold Voltage Model, 1988.
UCSD VLSICAD Lab