1. From Transistors To Computers

2. Gajski and Kuhn’s Y Chart Physical/Geometry Structural Behavioral Processor Hardware Modules ALUs, Registers Gates, FFs Transistors Systems Algorithms Register Transfer Logic Transfer Functions Architectural Algorithmic Functional Block Logic Circuit Rectangles Cell, Module Plans Floor Plans Clusters Physical Partitions

3. Discovery of the Electron -- 1898 J. J. Thomson Cathode Tube Cavendish Labs Electric Field -- “corpuscle”

4. Physical/Geometry Structural Behavioral Processor Hardware Modules ALUs, Registers Gates, FFs Transistors Systems Algorithms Register Transfer Logic Transfer Functions Architectural Algorithmic Functional Block Logic Circuit Rectangles Cell, Module Plans Floor Plans Clusters Physical Partitions The Transistor

5. The Vacuum Tube

6. The First Point-Contact Transistor 1947 Bell Labs Museum

7. The First Junction Transistor 1951 Bell Labs Lab model M1752 Outside the Lab

8. The Field Effect Transistor

9. The Transistor

10. Texas Instrument’s First IC -- 1958 Jack Kilby Robert Noyce Fairchild Intel

11. CMOS Circuits Physical/Geometry Structural Behavioral Processor Hardware Modules ALUs, Registers Gates, FFs Transistors Systems Algorithms Register Transfer Logic Transfer Functions Architectural Algorithmic Functional Block Logic Circuit Rectangles Cell, Module Plans Floor Plans Clusters Physical Partitions

12. Implementing Gates Relays Normally open Normally closed A B C A B C A B C nMOS transistor A-B closed when C = 1 (normally open) pMOS transistor A-B closed when C = 0 (normally closed)

13. CMOS Circuits

14. Logic Circuits X Y

17. Logic Circuits - Functions

18. Logic Circuits - Multiplexers

19. 4-line 2 x 1 Mux

20. n-line 2 x 1 Multiplexer Lab 1

21. library IEEE; use IEEE.std_logic_1164.all; entity mux2g is generic(width:positive); port ( a: in STD_LOGIC_VECTOR(width-1 downto 0); b: in STD_LOGIC_VECTOR(width-1 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR(width-1 downto 0) ); end mux2g; architecture mux2g_arch of mux2g is begin mux2_1: process(a, b, sel) begin if sel = '0' then y <= a; else y <= b; end if; end process mux2_1; end mux2g_arch; VHDL – n-line 2 x 1 Multiplexer

22. ALU1- Shifting, Incr, and Decr Lab 2 selyInstruction name “000”a + 11+ “001”a - 11- “010”not ainvert “011”shift left a2* “100”logic shift right aU2/ “101”arithmetic shift right a 2/ “110”all onestrue “111”all zerosfalse

23. Logic Circuits - Binary Adder

25. Logic Circuits - Full Adder

26. Binary Adder/Subtractor

27. ALU2 – Arithmetic and Logic Instructions Lab 3 selyInstruction name “000”a + b+ “001”b - a- “010”a and bAND “011”a or bOR “100”a xor bXOR “101”true if a = 0 false otherwise 0= “110”true if a < 0 false otherwise 0< “111”true if b > a (unsigned) false otherwise U>

28. ALU3 – Comparators Lab 4 selyInstruction name “000”true if b = a false otherwise = “001”true if b /= a false otherwise <> “010”true if b < a (unsigned) false otherwise U< “011”true if b > a (unsigned) false otherwise U> “100”true if b <= a (unsigned) false otherwise U<= “101”true if b < a (signed) false otherwise < “110”true if b > a (signed) false otherwise > “111”true if b <= a (signed) false otherwise <=

29. CMOS Circuits Physical/Geometry Structural Behavioral Processor Hardware Modules ALUs, Registers Gates, FFs Transistors Systems Algorithms Register Transfer Logic Transfer Functions Architectural Algorithmic Functional Block Logic Circuit Rectangles Cell, Module Plans Floor Plans Clusters Physical Partitions

30. Latches and Flip-Flops

33. State Machines

34. ALUs, Registers Physical/Geometry Structural Behavioral Processor Hardware Modules ALUs, Registers Gates, FFs Transistors Systems Algorithms Register Transfer Logic Transfer Functions Architectural Algorithmic Functional Block Logic Circuit Rectangles Cell, Module Plans Floor Plans Clusters Physical Partitions

35. An n-bit Register

36. A Function Unit (ALU1 – ALU3)

37. ALU

38. Datapath Physical/Geometry Structural Behavioral Processor Hardware Modules ALUs, Registers Gates, FFs Transistors Systems Algorithms Register Transfer Logic Transfer Functions Architectural Algorithmic Functional Block Logic Circuit Rectangles Cell, Module Plans Floor Plans Clusters Physical Partitions

39. Datapath

40. A Single-Cycle Processor Lab 5

41. Program Counter and Program Control Lab 6

42. Processor Physical/Geometry Structural Behavioral Processor Hardware Modules ALUs, Registers Gates, FFs Transistors Systems Algorithms Register Transfer Logic Transfer Functions Architectural Algorithmic Functional Block Logic Circuit Rectangles Cell, Module Plans Floor Plans Clusters Physical Partitions

43. Originally with Transistors

44. A Close Up

46. W8Z Processor

47. The FC16 Forth Core

48. Data Stack Lab 7

49. Return Stack Lab 8

50. The WC16 WHYP Core Lab 9

51. Multi-cycle Computer

52. Pipelined Computer

53. CISC Processor

54. Quantum Computer