1. Flip-Flops Lecture L8.2 Section 8.1

2. Recall the !S-!R Latch !S !R Q !Q 0 0 1 1 0 1 !S !R Q !Q 1 1 0 1 0 1 0 0 1 0 1 1 1 0 1 1 1 0 X Y nand 1 0 Set 1 0 Store 0 1 Reset 1 1 Disallowed Q 0 !Q 0

3. Edge-triggered D Flip-flop 0 1 1 1 0 1

4. 1 0 1 0 1 1 0 1

5. 1 0 1 0 1 0 1 1

6. 1 0 0 1 1 0 1 0

7. 1 1 0 0 1 0 0 1

8. 1 1 0 1 1 0 0 1

9. 0 1 1 1 0 1 0 1

12. Edge-triggered D Flip-flop with asynchronous preset and clear

14. D Flip-Flop CLK DQ !Q 0 0 1 1 1 0 X 0 Q 0 !Q 0 D CLK Q !Q D gets latched to Q on the rising edge of the clock. Positive edge triggered

15. Each Xilinx 95108 macrocell contains a D flip-flop Controlled inverter

16. Each Xilinx 95108 macrocell contains a D flip-flop Note asynchronous preset x Q.AP = x Note asynchronous reset Q.AR = y y Q.D = z z

17. Divide-by-2 Counter CLK Q0 Q0.D = !Q0 CLK DQ !Q Q0.D = !Q0 Q0 Q0.D !Q0

18. MODULE div2cnt TITLE 'Divide By 2 Counter' DECLARATIONS " INPUT PINS " PB PIN 70; " push-button switch (clock) " OUTPUT PINS " Q0 PIN 44 ISTYPE 'reg buffer'; " LED 16 div2cnt.abl CLK DQ !Q Q0.D = !Q0 Q0 Q0.D !Q0 Registered Buffer output

19. EQUATIONS Q0.C = PB; Q0.D = !Q0; test_vectors(PB -> Q0).C. -> 1;.C. -> 0;.C. -> 1;.C. -> 0;.C. -> 1;.C. -> 0; END div2cnt.abl (cont’d) CLK DQ !Q Q0.D = !Q0 Q0 Q0.D !Q0.C. means clock goes LO-HI-LO Power-on output Q0 = 0

20. A 1-Bit Register

21. MODULE reg1bit TITLE '1-bit register, R. Haskell, 10/13/02' DECLARATIONS hex7seg interface([D3..D0] -> [a,b,c,d,e,f,g]); d7R FUNCTIONAL_BLOCK hex7seg; " INPUT PINS " PB PIN 70; " push-button switch (clock) LOAD PIN 11;" switch S6:1 clear PIN 7;" switch S6:2 INP0 PIN 1;" switch S7:4 " OUTPUT PINS " Q0 PIN 44 ISTYPE 'reg buffer'; " LED 16 [a,b,c,d,e,f,g] PIN 15,18,23,21,19,14,17 ISTYPE 'com'; " Rightmost (units) 7-segment LED display

22. EQUATIONS Q0.C = PB; Q0.AR = clear; Q0.D = Q0 & !LOAD # INP0 & LOAD; [a,b,c,d,e,f,g] = d7R.[a,b,c,d,e,f,g]; d7R.D0 = Q0; d7R.[D3..D1] = [0,0,0]; test_vectors([PB,clear,LOAD,INP0] -> Q0) [.C.,1,0,1] -> 0; [.C.,0,1,1] -> 1; [.C.,0,0,0] -> 1; [.C.,0,1,0] -> 0; [.C.,0,0,1] -> 0; [.C.,0,1,1] -> 1; [.C.,0,0,0] -> 1; [.C.,0,0,1] -> 1; [.C.,0,1,0] -> 0; END

23. A 4-Bit Register

24. 4-Bit Register reset to 1010

25. MODULE reg4bit5 INTERFACE (clk,reset,load,[IN3..IN0] -> [Q3..Q0]); TITLE ',, ' DECLARATIONS " Input Pins " clk PIN ; reset PIN ; load PIN ; IN3..IN0 Pin ; INP = [IN3..IN0]; " 4-bit input data " Output Pins " Q3..Q0 PIN ISTYPE 'reg buffer'; Q = [Q3..Q0]; " 4-bit register EQUATIONS Q.c = clk; [Q2, Q0].ar = reset; [Q3, Q1].ap = reset; "reset Q = 5 Q.d = INP & load # Q & !load; END reg4bit5

26. J-K Flip-flops Q.D = J & !Q # !K & Q

27. J-K Flip-flops

28. T Flip-flops Q.D = T $ Q

29. T Flip-flops

30. MODULE Tdiv2cnt TITLE 'Divide By 2 Counter using T flip-flop' DECLARATIONS " INPUT PINS " PB PIN 70; " push-button switch (clock) " OUTPUT PINS " Q0 PIN 44 ISTYPE 'reg buffer'; " LED 16 EQUATIONS Q0.C = PB; Q0.T = 1; test_vectors(PB -> Q0).C. -> 1;.C. -> 0;.C. -> 1;.C. -> 0;.C. -> 1;.C. -> 0; END 1