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Verilog HDL (Behavioral Modeling) Bilal Saqib. Behavioral Modeling.

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Presentation on theme: "Verilog HDL (Behavioral Modeling) Bilal Saqib. Behavioral Modeling."— Presentation transcript:

1 Verilog HDL (Behavioral Modeling) Bilal Saqib

2 Behavioral Modeling

3 Structured Procedures

4 Procedural Blocks Procedural Blocks are constructed from the following components. ◦Procedural Assignment Statements ◦High-Level Constructs

5 Procedural Assignments

6 Procedural Execution Control Execution of Procedural Blocks can be specified in different ways ◦Simple Delays: #  Specify delay before and after execution for a number of time steps. ◦Edge-Sensitive Controls: always @ ( )  Execution occurs only at a signal edge. Optional keywords “posedge” or “negedge” can be used to specify signal edge for execution.

7 NonBlocking v Blocking Assignments

8

9 Conditional Statements: if else

10 Conditional Statements: case

11 casex and casez

12 Looping Statements: repeat

13 Looping Statements: while

14 Looping Statements: forever

15 Looping Statements: for

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