1. Cache Memory Midterm 2 Revision 2 Prof. Sin-Min Lee Department of Computer Science

2. The Processor Picture

3. The Five Classic Components of a Computer Control Datapath Memory Processor Input Output

5. von Neumann Architecture Princeton Address Pointer Arithmetic Logic Unit (ALU) Memory Program Counter Pc = Pc + 1 Data/Instructions Featuring Deterministic Execution

9. Cache Memory Physical memory is slow (more than 30 times slower than processor) Cache memory uses SRAM chips. –Much faster –Much expensive –Situated closest to the processor Can be arranged hierarchically –L1 cache is incorporated into processor –L2 cache is outside

10. Cache Memory This photo shows level 2 cache memory on the Processor board, beside the CPU

11. Cache Memory - Three Levels Architecture Address Pointer Memory Multi- Gigabytes Large and Slow 160 X 16X L3 Cache Memory Cache Control Logic L2 Cache Memory L1 Cache Memory 2X 8X 16 Megabytes 128 Kilobytes 32 Kilobytes 2 Gigahertz Clock Featuring Really Non-Deterministic Execution

13. Cache (1) Is the first level of memory hierarchy encountered once the address leaves the CPU –Since the principle of locality applies, and taking advantage of locality to improve performance is so popular, the term cache is now applied whenever buffering is employed to reuse commonly occurring items We will study caches by trying to answer the four questions for the first level of the memory hierarchy

17. Subtract by Summation Subtraction with complement is done with binary numbers in a similar way. Using two binary numbers X=1010100 and Y=1000011 We perform X-Y and Y-X

18. X-Y X=1010100 2’s com. of Y=0111101 Sum= 10010001 Answer=0010001

19. Y-X Y=1000011 2’s com. of X=0101100 Sum=1101111 There’s no end carry: answer is negative --- 0010001 (2’s complement of 1101111)

20. How To Represent Signed Numbers Plus and minus signs used for decimal numbers: 25 (or +25), -16, etc..For computers, it is desirable to represent everything as bits. Three types of signed binary number representations: 1.signed magnitude, 2.1’s complement, and 3.2’s complement

21. 1. signed magnitude In each case: left-most bit indicates sign: positive (0) or negative (1). Consider 1. signed magnitude: 00001100 2 = 12 10 Sign bitMagnitude 10001100 2 = -12 10 Sign bitMagnitude

22. 2. One’s Complement Representation The one’s complement of a binary number involves inverting all bits. To find negative of 1’s complement number take the 1’s complement of whole number including the sign bit.To find negative of 1’s complement number take the 1’s complement of whole number including the sign bit. 00001100 2 = 12 10 Sign bitMagnitude 11110011 2 = -12 10 Sign bit1’complement

23. 3. Two’s Complement Representation The two’s complement of a binary number involves inverting all bits and adding 1. To find the negative of a signed number take the 2’s the 2’s complement of the positive number including the sign bit. 00001100 2 = 12 10 Sign bitMagnitude 11110100 2 = -12 10 Sign bit2’s complement

24. The rule for addition is add the two numbers, including their sign bits, and discard any carry out of the sign (leftmost) bit position. Numerical examples for addition are shown below. Example: + 600000110- 611111010 +1300001101+1300001101 +1900010011+700000111 +600000110-611111010 -1311110011-1311110011 -711111001-1911101101 In each of the four cases, the operation performed is always addition, including the sign bits. Only one rule for addition, no separate treatment of subtraction. Negative numbers are always represented in 2’s complement. Sign addition in 2’s complement

25. Arithmetic Subtraction A subtraction operation can be changed to an addition operation if the sign of the subtrahend is changed. (±A) - (+B) = (±A) + (-B) (±A) - (-B) = (±A) + (+B)

26. Arithmetic Subtraction Consider the subtraction of (-6) - (-13) = +7. In binary with eight bits this is written as 11111010 - 11110011. The subtraction is changed to addition by taking the 2’s complement of the subtrahend (- 13) to give (+13). In binary this is 11111010 + 00001101 = 100000111. Removing the end carry, we obtain the correct answer 00000111 (+ 7).

27. 4 to 1 MUX 2 - 4 Decoder Control DataFlow D3:D0 4 Sel(3:0) 4 S1:S0 2 Dout

28. 4-to-1 MUX (Gate level) Three of these signal inputs will always be 0. The other will depend on the data value selected Control Section

29. Until now, we have examined single-bit data selected by a MUX. What if we want to select m-bit data/words?  Combine MUX blocks in parallel with common select and enable signals Example: Construct a logic circuit that selects between 2 sets of 4-bit inputs (see next slide for solution). Multiplexer (cont.)

30. Example: Quad 2-to-1 MUX Uses four 4-to-1 MUXs with common select (S) and enable (E). Select line chooses between A i ’ s and B i ’ s. The selected four- wire digital signal is sent to the Y i ’ s Enable line turns MUX on and off (E=1 is on).

31. Implementing Boolean functions with Multiplexers Any Boolean function of n variables can be implemented using a 2 n-1 -to-1 multiplexer. A MUX is basically a decoder with outputs ORed together, hence this isn ’ t surprising. The SELECT signals generate the minterms of the function. The data inputs identify which minterms are to be combined with an OR.

32. Example F(X,Y,Z) = X’Y’Z + X’YZ’ + XYZ’ + XYZ = Σm(1,2,6,7) 2 2 -to-1 MUXThere are n=3 inputs, thus we need a 2 2 -to-1 MUX The first n-1 (=2) inputs serve as the selection linesThe first n-1 (=2) inputs serve as the selection lines

33. Efficient Method for implementing Boolean functions For an n-variable function (e.g., f(A,B,C,D)): –Need a 2 n-1 line MUX with n-1 select lines. –Enumerate function as a truth table with consistent ordering of variables (e.g., A,B,C,D) –Attach the most significant n-1 variables to the n-1 select lines (e.g., A,B,C) –Examine pairs of adjacent rows (only the least significant variable differs, e.g., D=0 and D=1). –Determine whether the function output for the (A,B,C,0) and (A,B,C,1) combination is (0,0), (0,1), (1,0), or (1,1). –Attach 0, D, D ’, or 1 to the data input corresponding to (A,B,C) respectively.

34. Another Example Consider F(A,B,C) =  m(1,3,5,6). We can implement this function using a 4-to-1 MUX as follows. The index is ABC. Apply A and B to the S 1 and S 0 selection inputs of the MUX (A is most sig, S 1 is most sig.) Enumerate function in a truth table.

35. MUX Example (cont.) ABCF 0000 0011 0100 0111 1000 1011 1101 1110 When A=B=0, F=C When A=0, B=1, F=C When A=1, B=0, F=C When A=B=1, F=C’

36. MUX implementation of F(A,B,C) =  m(1,3,5,6) A B C C C C’ F

37. These pictures have errors.

38. 2 Input Multiplexor Inputs: I 0 and I 1 Selector: S Output: O If S is a 0: O=I 0 If S is a 1: O=I 1 Mux I0I0 I1I1 O S

39. 2-Mux Logic Design I1I1 I0I0 S O I 0 && !S I 1 && S

40. 4 Input Multiplexor Inputs: I 0 I 1 I 2 I 3 Selectors: S 0 S 1 Output: O Mux I0I0 I2I2 O S0S0 S0S0 S1S1 O 00I0I0 01I1I1 10I2I2 11I3I3 I1I1 I3I3 S1S1

41. One Possible 4-Mux 2-Decoder I0I0 I1I1 I2I2 I3I3 S0S0 S1S1 O

42. Adder We want to build a box that can add two 32 bit numbers. –Assume 2s complement representation We can start by building a 1 bit adder.

43. Addition We need to build a 1 bit adder –compute binary addition of 2 bits. We already know that the result is 2 bits. ABO0O0 O1O1 0000 0101 1001 1110 A + B O 0 O 1 This is addition!

44. One Implementation A B O0O0 !A B A !B O1O1 A && B (!A && B) || (A && !B)

45. Binary addition and our adder What we really want is something that can be used to implement the binary addition algorithm. –O 0 is the carry –O 1 is the sum 01001 + 01101 10110 11 Carry

46. What about the second column? We are adding 3 bits –new bit is the carry from the first column. –The output is still 2 bits, a sum and a carry 01001 + 01101 10110 11 Carry

47. Truth Table for Addition ABCarry In Carry Out Sum 00000 00101 01001 01110 10001 10110 11010 11111

49. Synchronous Sequential Circuit with T Flip-Flop -- Figure 8.12

50. Timing Diagram Figure 8.13

51. State Table and State Diagram

52. K-Maps for Example

53. Example 2.Synchronous Sequential Circuit with JK Flip-flops

54. Timing Diagram and State Table for Example 2

55. K-Maps for Example 2

56. Generating the State Table From K-maps -- Example 2

57. Example 3.Synchronous Sequential Circuit Synthesis

58. Introductory Synthesis Example -- Example 3

59. Flip-flop Input Tables -- Example 3

60. Generating the JK Flip-flop Excitation Maps -- Example 3

61. Clocked JK Flip-Flop Implementation -- Example 3

62. Application Equation Method for Deriving Excitation Equations -- Example 3

64. Registers Two independent flip-flops with clear and preset

65. Using T Flip Flop and JK Flip Flop log 2 4 = 2, so 2 flip flops are needed to implement this FSA

66. Step 1 - Translate diagram into State Table

67. Step 2 - Create maps for T and JK

68. Step 3 - Determine T, J, and K equations

69. Step 4 - Draw resulting diagram