1. Counters Discussion 12.1 Example 33

2. Counters 3-Bit, Divide-by-8 Counter 3-Bit Behavioral Counter in Verilog Modulo-5 Counter An N-Bit Counter

3. 3-Bit, Divide-by-8 Counter

4. Divide-by-8 Counter s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1 s3 0 1 1 1 0 0 s4 1 0 0 1 0 1 s5 1 0 1 1 1 0 s6 1 1 0 1 1 1 s7 1 1 1 0 0 0 State q2 q1 q0 D2 D1 D0 Present state Next state

5. Divide-by-8 Counter q2 q1 q0 00011110 0 1 11 1 1 D2 D2 = ~q2 & q1 & q0 | q2 & ~q1 | q2 & ~q0 s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1 s3 0 1 1 1 0 0 s4 1 0 0 1 0 1 s5 1 0 1 1 1 0 s6 1 1 0 1 1 1 s7 1 1 1 0 0 0 State q2 q1 q0 D2 D1 D0 Present state Next state

6. Divide-by-8 Counter q2 q1 q0 00011110 0 1 1 1 1 1 D1 D1 = ~q1 & q0 | q1 & ~q0 s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1 s3 0 1 1 1 0 0 s4 1 0 0 1 0 1 s5 1 0 1 1 1 0 s6 1 1 0 1 1 1 s7 1 1 1 0 0 0 State q2 q1 q0 D2 D1 D0 Present state Next state

7. Divide-by-8 Counter q2 q1 q0 00011110 0 1 1 1 1 1 D0 D0 = ~q0 s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1 s3 0 1 1 1 0 0 s4 1 0 0 1 0 1 s5 1 0 1 1 1 0 s6 1 1 0 1 1 1 s7 1 1 1 0 0 0 State q2 q1 q0 D2 D1 D0 Present state Next state

8. Divide-by-8 Counter A Divide by 8 counter circuit using D Flip-flops

9. module count3a ( input wire clr, input wire clk, output reg [2:0] q ); wire [2:0] D ; assign D[2] = ~q[2] & q[1] & q[0] | q[2] & ~q[1] | q[2] & ~q[0]; assign D[1] = ~q[1] & q[0] | q[1] & ~q[0]; assign D[0] = ~q[0]; // Three D flip-flops always @(posedge clk or posedge clr) if(clr == 1) q <= 0; else q <= D; endmodule

10. count3a Simulation

11. Counters 3-Bit, Divide-by-8 Counter 3-Bit Behavioral Counter in Verilog Modulo-5 Counter An N-Bit Counter

12. 3-Bit Counter always @(posedge clk or posedge clr) begin if(clr == 1) q <= 0; else q <= q + 1; end Behavior count3 clr clk Q[2:0]

13. module count3b ( input wire clr, input wire clk, output reg [2:0] q ); // 3-bit counter always @(posedge clk or posedge clr) begin if(clr == 1) q <= 0; else q <= q + 1; end endmodule count3b.v Asynchronous clear Output count increments on rising edge of clk

14. count3b Simulation

15. Counters 3-Bit, Divide-by-8 Counter 3-Bit Behavioral Counter in Verilog Modulo-5 Counter An N-Bit Counter

16. module mod5cnt ( input wire clr, input wire clk, output reg [2:0] q ); // modulo-5 counter always @(posedge clk or posedge clr) begin if(clr == 1) q <= 0; else if(q == 4) q <= 0; else q <= q + 1; end endmodule

17. mod5cnt Simulation

18. Counters 3-Bit, Divide-by-8 Counter 3-Bit Behavioral Counter in Verilog Modulo-5 Counter An N-Bit Counter

19. module counter #(parameter N = 8) (input wire clr, input wire clk, output reg [N-1:0] q ); // N-bit counter always @(posedge clk or posedge clr) begin if(clr == 1) q <= 0; else q <= q + 1; end endmodule defparam cnt16.N = 16; counter cnt16(.clr(clr),.clk(clk),.q(q));

20. counter Simulation N = 8