1. Chapter 10 Hardware Details on the 8088 Objectives: The general specification on the 8088 microprocessors The processor’s control signal names and specifications General signal relationship and timings Methods by which the 8088 can interface with external devices The external interrupt signals and their operations The 8088 bus controller The method used to access an 8085 peripheral EE314 Microprocessor Systems Based on "An Introduction to the Intel Family of Microprocessors" by James L. Antonakos

2. 10.3 CPU pin descriptions GND A14 A13 A12 A11 A10 A9 A8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND Vcc A15 A16/S3 A17/S4 A18/S5 A19/S6 ___ SS0(HIGH) ___ MN/MX ___ RD ___ ____ HOLD(RQ/GT0) ___ ____ HLDA (RQ/GT1) ___ ______ WR(LOCK) __ __ IO/M(S2) __ __ DT/R(S1) ____ __ DEN(S0) ALE(QS0) _____ INTA(QS1) _____ TEST READY RESET 140 8088 2021 Minmode operation signals (MN/MX=1) Maxmode operation signals (MN/MX=0) Address Bus (outputs) Time-multiplexed Address (outputs)/ Data Bus (bidirectional) Hardware interrupt requests (inputs) 2...5MHz, 1/3 duty cycle (input) 0V=“0”, reference for all voltages 5V±10% Time- multiplexed Address Bus /Status signals (outputs) Status signals (outputs) Operation Mode, (input): 1 = minmode (8088 generates all the needed control signals for a small system), 0 = maxmode (8288 Bus Controller expands the status signals to generate more control signals) Interrupt acknowledge (output) Control Bus (in,out)

3. 10.3 CPU pin descriptions 8088 Status Signals Comparison of NMI and INTR 8088 Signal Summary IOWR IORD MEMWR MEMRD RD WR IO/M Decoding 8088 memory and I/O read/write signals

4. 10.4 The 8284 Clock Generator RDY1 RDY2 EFI CLK F/C CSYNC AEN1 AEN2 8284 ASYNC X1 READY X2 RES RESET 5V READY1 READY2 5V 10MHz 4K7 2X510 5V 10  F 100K 1N4148 CLK 8088 READY RESET t RES [V] t RESET 1L 0L 0 = crystal oscillator 1 = TTL clock on EFI, synchronized on CSYNC t X1,2 [V] qualifiers for READY1,-2 1 = one WAIT state forced by READY 0 = forces the  P to froze the current bus cycle inserting WAIT STATES (all signals keep their values), allowing slower devices time to properly answer. CLK 1/3 f osc 1/3 duty cycle

5. DEN DT/R MRDC ALE MWTC S0 IORC S1 8288 IOWC S2 INTA AMWC AIOWC IOB AEN CEN 10.5 The 8288 Bus Controller 8286 OE T 8282 STB OE D Q LE CPU Address Bus (A16-A19, if needed, should be latched the same way like AD0-AD7) CPU Data Bus A8-A15 AD0-AD7 8088 S0 S1 S2 Memory ReaD Command Memory WriTe Command Input/Output Read Command Input/Output Write Command INTerrupt Acknowledge Advanced Memory Write Command Advanced Input/Output Write Command Status Signals (codify the bus cycle type) Control Bus Max one active at a time, identifying Memory vs. I/O and Read vs. Write Identify the Memory Byte (one of 2 20 (2 16 in example)) OR the I/O port (one of 2 16 ) to be read OR write in the current bus cycle Advanced Write Commands, providing additional access time for the selected circuit Data to be transferred in the current bus cycle Data Transmit/Receive 5V CLK Address Latch Enable Data Enable Command Enable Address Enable I/O Bus only 74LS244 G1 G2

6. 10.6 System Time Diagrams - CPU Bus Cycle T2T2 T3T3 TWTW T4T4 Read Cycle (instruction fetch and memory operand read) A 8 - A 15 Address latches store the actual values Memory Cycle (I/O cycle is similar but IO/M = 1) S 3 - S 6 Tri-state A 16 -A 19 A 0 - A 7 T1T1 CLK ALE IO/M A 16 - A 19 A 8 - A 15 RD AD 0 - AD 7 DT/R READY DEN Direction “READ” for the Data BufferEnables Data Buffer WR AD 0 - AD 7 DT/R Write Cycle (memory operand write) A 0 - A 7 D 0 - D 7 (Data out) DEN Direction “READ” for the Data Buffer Enables Data Buffer Memory reads Data Bus The slow device drives READY= 0 the  P samples READY (if 0 a WAIT state follows) D 0 - D 7 (Data in)  P reads Data Bus

7. 10.6 System Time Diagrams - INT and HOLD T4T4 T1T1 HOLD/HLDA Timing CLK HOLD HLDA HOLD state: the  P releases the Address, Data, Control and Status buses (these pins are tri-sated (high impedance) only after ending the current bus cycle CLK INTA AD 0 - AD 7 T2T2 T3T3 T4T4 T1T1 INT type Tri-state Minmode Interrupt acknowledge timing a single INTA cycle in minmode. CLK LOCK INTA AD 0 - AD 7 T2T2 T3T3 T4T4 T1T1 T2T2 T3T3 T4T4 T1T1 INT type First INTA cycle Second INTA cycle Tri-state Maxmode Interrupt acknowledge timing two INTA cycles in maxmode, the device requesting INT has to drive the “INT type” on the Data Bus, during the second cycle. Prevents  P to enter a HOLD state

8. 10.7 Personal Computer Bus Standards CPU Memory Bus Cash Memory Memory Controller  P Bus Main Memory I/O Bus Controller Plug-in I/O Boards I/O Bus Motherboard I/O Circuits CPU Memory I/O  P Bus CPU Cash Memory  P Bus Memory Bus Memory Controller Main Memory Bridge Controller Motherboard- and Fast Plug-in I/O Circuits PCI (Mezzanine) Bus I/O Bus Controller I/O Bus Slow Plug-in I/O Boards Simple  P System Architecture PCI (Peripheral Component Interconnect bus) based Architecture Medium Complexity PC Architecture - ISA = Industry Standard Architecture (8 data bits = PC-XT bus, or 16 data bits = PC-AT bus) - EISA = Extended ISA - MCA = Micro Channel Architecture (only IBM)

9. 10.7 Personal Computer Bus Standards - ISA Bus GND RESETDRV +5V IRQ2(9) -5V DRQ2 -12V 0WS +12V GND -SMEMW -SMEMR -IOW -IOR -DACK3 DRQ3 -DACK1 DRQ1 -REFRESH SYSCLK IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 -DACK2 TC BALE +5V OSC GND I/O CH CK SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 I/O CH RDY AEN SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 B1A1 B5A5 B10A10 B15A15 B20A20 B25A25 B30A30 B31A31 -MEMCS16 -IOCS16 IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 -DACK0 DRQ0 -DACK5 DRQ5 -DACK6 DRQ6 -DACK7 DRQ7 +5V -MASTER GND SBHE LA23 LA22 LA21 LA20 LA19 LA18 LA17 -MEMR -MEMW SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 D1C1 D5C5 D10C10 D15C15 D18C18 D18D1 C18C1 B31B1 A31A1 Back side of PC