1. 1 Lucas-Lehmer Primality Tester Presentation 6 March 1st 2006 Team: W-4 Nathan Stohs W4-1 Brian Johnson W4-2 Joe Hurley W4-3 Marques Johnson W4-4 Design Manager: Prateek Goenka Overall Objective: Modular Arithmetic unit with a creative use This is my presentation, there are others like it but this one is mine

2. 2 Status Finished –Project Chosen –C simulations –Behavioral Verilog –Structural Verilog –Revised Floor Plan –Schematics –Pathmill Simulation of Top Level In Progress –Layout –Layout Simulations To Do –More Layout –Layout Simulations

3. 3 Transistor Counts ModuleTransistor Count Count2,664 Mod_Multiply11,120 Mod_Add1282 Partial Products8,676 Counter266 Dff_re (16)896 Sub_16704 Compare36 Mod_P1,280 Top Level Flops896 FSM700 Total17,400

4. 4 Power Consumption ModulePower Count53.81 uW Mod_Multiply? Mod_Add128.8 uW Partial Products368 uW Counter36.77 uW Dff_re (16)260 uW Compare149.2 pW Mod_P397.6 uW Top Level Flops39.6 uW FSM? Top (100ns)636.2 uW

5. 5 Sub_16

6. 6 X = 32Y = 7OUT = 25 Sub_16 Simulation

7. 7 Top Simulation S1 = (4 * 4 - 2) mod 127 = 14

8. 8 Top Simulation S2 = (14 * 14 - 2) mod 127 = 67

9. 9 Pathmill Results Shift_Left =.610 ns Shift_Right =.610 ns Mod_P =.610 ns Mod_Add = 8.993 ns Partial_Products = 5.135 ns Longest Path from Top Simulation = 12.703ns

10. 10 Block Area Estimates (Updated) ModuleArea (μm 2 ) Count13,200 Mod_Mult54,500 Sub_163,500 Compare200 Mod_P6,500 Top Level Flops4,400 Mod_add6,528 FSM3,500

11. 11 Updated Floorplan

12. 12 What’s Next Continue Layout Simulate Layout Power Estimations for Layout

13. 13 Questions?