1. Team W3: Anthony Marchetta Derek Ritchea David Roderick Adam Stoler Milestone 8: March 24th Chip Level Layout Overall Project Objective: Design an Air-Fuel Ratio Controller for a small gasoline engine with low emissions and low cost Design Manager: Steven Beigelmacher

2. Logos are cool!!

3. Status Design Proposal (done) Architecture (done) High Level C Simulation Behavioral Verilog & Test Bench Floorplan & Structural Verilog Gate Level Design (done) Top Level Schematic Verification Component Layout (done) Analog simulation of SRAM and ROM Layout of all components Component Simulation (done) Smaller Multiplier completed Chip-Level Layout(80%) Small amount of routing left to do Still to be done Top level simulation

4. 12bit Input Reg 8X10 SRAM Value Look-up 12bit Input Reg Engine Speed Manifold Pressure 12bit Input Reg Throttle Position Fixed Point Array Multiplier 2:1Mu x 12bit Output Register Control ROM 12bit Input Reg %Oxygen 7X4 SRAM Comparator Look-up 4:1Mux = R0 12bit Register Win Sin[0:1] 2:1Mu x Rcomp Sin[0:1] Index[0:4] Write R1 R2 RowComp[0]RowComp[1] Srow1 Srow2 RowComp[2] 3bit Reg Wcol Index[0:6] Write Rtable 2:1Mu x Scol ColTable[0:3] 2:1Mu x Scol Valid Wmult1 Wmult2 Smult 5bit State Reg Next[0:4] Wout PulseOut[0:11]

5. Design Decisions Decoder design –Used Metal3, did not abut with RAM or ROM –Do Over? pros = use a more conventional method, use lower layer metals, easier to route across. cons = incredibly time consuming, doesn't save any chip area. –We decided not to redo the decoders.

6. Multiplier (old) 58,706 um2 Lots of white space Awkward Shape

7. Multiplier (new) 22,694 um2 Less white space Rectangular Shape

8. Multiplier Simulation Prop time = 1.08ns

9. Multiplier Simulation Prop time = 1.08ns Rise time = 214.5 ps

10. Verilog Re-Verification

11. Mask – Poly & Active

12. Mask – Metal 1

13. Mask – Metal 2

14. Mask – Metal 3

15. Mask – Metal 4

16. Top Level Layout (old) 385X340(µm)

17. Top Level Layout (new) 383x273(µm)

18. Old Layout 340 x 385 (µm) 130,900 (µm 2 ) Aspect Ratio: 1.13 Trans. Density:.124 Tran/ µm 2 New Layout 383 x 273 (µm) 104,559 (µm2 ) Aspect Ratio: 1.4 Trans. Density:.167 Tran/ µm 2 Vs. Transistor Count = 17,465 Clock Speed 1MHz – speed is not our goal

19. Questions????