1. 1 Advanced Digital Design Asynchronous Design: Research Concept by A. Steininger and M. Delvai Vienna University of Technology

2. 2 Research Concept FSL Reference Hardware (MA)

3. 3 Reference Hardware Outcome: Aspear2 Four stage pipeline Four stage pipeline Configurable data path (16 / 32 bits) Configurable data path (16 / 32 bits) AMBA interface AMBA interfaceChallenges: Handle improved complexity Handle improved complexity Asynchronous AMBA interface Asynchronous AMBA interface Tools interface Tools interface

4. 4 Research Concept FSL Design Flow Optimization (MA) Reference Hardware (MA)

5. 5 Design Flow Optimization Current design flow requires an “FSL-based” VHDL style code: Current design flow requires an “FSL-based” VHDL style code: manual register placement manual register placement explicit handshake signal connection explicit handshake signal connection stable function stable function Improved design flow Improved design flow use synchronous designs as starting point use synchronous designs as starting point synthesize design using an AND-OR-INV library synthesize design using an AND-OR-INV library replace standard gates with corresponding FSL gates replace standard gates with corresponding FSL gates perform automatic handshake connections and phase inverter insertion perform automatic handshake connections and phase inverter insertion resynthesize the design resynthesize the design

6. 6 Design Flow Optimization Outcome Automatic conversion of synchronous designs to FSL circuits Automatic conversion of synchronous designs to FSL circuitsChallenges: Identification of circuit structures Identification of circuit structures Placement of phase-inverters Placement of phase-inverters

7. 7 Research Concept FSL Basic Gates Optimization (MA) Design Flow Optimization (MA) Reference Hardware (MA)

8. 8 Basic Gates Optimization Outcome: Efficient FSL gates for FPGA technologies FPGA technologies ASIC technologies ASIC technologiesChallenge: Preserve delay insensitivity Preserve delay insensitivity Reduce size/transistor count Reduce size/transistor count Limit the performance penalty Limit the performance penalty

9. 9 Research Concept FSL Fault Tolerance: RADIAL (Project) Basic Gates Optimization (MA) Design Flow Optimization (MA) Reference Hardware (MA)

10. 10 Fault Tolerance: RADIAL Generic statement: Generic statement: FSL circuits tolerate transient fault(s) due to the inherent consistency check FSL circuits tolerate transient fault(s) due to the inherent consistency check Register (00) (11) (00) (11) (00) (10) (01) (10)

11. 11 Fault Tolerance : RADIAL Generic statement: Generic statement: FSL circuits tolerate transient fault(s) due to the inherent consistency check FSL circuits tolerate transient fault(s) due to the inherent consistency check Register (00) (11) (00) (11) (00) (10) (01) (10)

12. 12 Fault Tolerance : RADIAL Generic statement: Generic statement: FSL circuits tolerate transient fault(s) due to the inherent consistency check FSL circuits tolerate transient fault(s) due to the inherent consistency check Register (00) (11) (00) (11) (00) (10) (01) (10)

13. 13 Fault Tolerance : RADIAL Generic statement: Generic statement: FSL circuits tolerate transient fault(s) due to the inherent consistency check FSL circuits tolerate transient fault(s) due to the inherent consistency check Register (00) (11) (00) (11) (00) (10) (01) (10)

14. 14 Fault Tolerance : RADIAL Generic statement: Generic statement: FSL circuits tolerate transient fault(s) due to the inherent consistency check FSL circuits tolerate transient fault(s) due to the inherent consistency check Register (00) (11) (00) (11) (00) (10) (00) (10)

15. 15 Fault Tolerance : RADIAL Generic statement: Generic statement: FSL circuits tolerate transient fault(s) due to the inherent consistency check FSL circuits tolerate transient fault(s) due to the inherent consistency check Register (00) (11) (00) (11) (00) (10) (01) (10)

16. 16 Fault Tolerance : RADIAL Generic statement: Generic statement: FSL circuits tolerate transient fault(s) due to the inherent consistency check FSL circuits tolerate transient fault(s) due to the inherent consistency check Register (00) (11) (00) (01) (00) (10) (01) (10)

17. 17 Fault Tolerance : RADIAL Generic statement: Generic statement: FSL circuits tolerate transient fault(s) due to the inherent consistency check FSL circuits tolerate transient fault(s) due to the inherent consistency check Register (00) (11) (00) (10) (00) (10) (01) (10)

18. 18 Fault Tolerance : RADIAL Generic statement: Generic statement: FSL circuits tolerate transient fault(s) due to the inherent consistency check FSL circuits tolerate transient fault(s) due to the inherent consistency check Register (00) (11) (00) (10) (01) (10) (01) (10)

19. 19 Fault Tolerance : RADIAL Also combinational logic masks transient faults Also combinational logic masks transient faults FSL tolerates more than one transient fault at the same time FSL tolerates more than one transient fault at the same time But: But: If the critical path is affected, then the transient fault will not be masked However FSL shows still a higher robustness compared to synchronous logic However FSL shows still a higher robustness compared to synchronous logic

20. 20 Fault Tolerance : RADIAL Possible improvements: Hardware redundancy Hardware redundancy Duplication of the critical path only? Duplication of the critical path only? Temporal redundancy Temporal redundancy Two phases => stuck @ faults detectable Two phases => stuck @ faults detectable Additional monitor for invalid transitions Additional monitor for invalid transitions …

21. 21 Fault Tolerance : RADIAL Outcome Demonstrate, that FSL is able to tolerate multiple faults Demonstrate, that FSL is able to tolerate multiple faults Guarantee, that un-tolerated faults result in a deadlock Guarantee, that un-tolerated faults result in a deadlockChallenges: Improve fault tolerance as far as possible Improve fault tolerance as far as possible Trade-off: Performance vs area overhead vs fault tolerance Trade-off: Performance vs area overhead vs fault tolerance

22. 22 Research Concept FSL Selfhealing FSL Circuits (PhD) Fault Tolerance: RADIAL (Project) Basic Gates Optimization (MA) Design Flow Optimization (MA) Reference Hardware (MA)

23. 23 Self-healing FSL Circuits Motivation Increasing defect rate due to miniaturization Increasing defect rate due to miniaturization FSL drawback FSL drawback A single stuck at fault cause a deadlock A single stuck at fault cause a deadlock  Have to be “removed” in order to achieve high reliable circuits  “Self-healing” is required

24. 24 Selfhealing FSL Circuits Task for self healing 1.Error detection 2.Error localization 3.Mitigate error 4.Recovery

25. 25 Detection and Localization Detection approaches Detection approaches Codes (Partity, CRC, …) Codes (Partity, CRC, …) Hardware redundancy (TMR, NMR, …) Hardware redundancy (TMR, NMR, …) Temporal redundancy Temporal redundancy Localization Localization Strongly related to the detection approach Strongly related to the detection approach Problem: granularity of the localization Problem: granularity of the localization

26. 26 Detection and Localization with FSL Detection: (Permanent) fault causes a deadlock: Detection: (Permanent) fault causes a deadlock: => Can be recognized using a watchdog Localization: Localization: => Can be done by identifying bubbles, when a deadlock occurred Control Unit LATCHLATCH f(x) LATCHLATCH LATCHLATCH LATCHLATCH

27. 27 Mitigate Options: Rebuild the circuit: Rebuild the circuit: Bitstream manipulation Bitstream manipulation Runtime synthesis Runtime synthesis Pre-synthesized configurations Pre-synthesized configurations  Require FPGA based plattforms Self-healing cells Self-healing cells

28. 28 Self-healing Cells First approach First approach AND MUXMUX Control Problem: Also interconnects may be faulty Problem: Also interconnects may be faulty

29. 29 Self-healing Cells Second approach Second approach AND ROUTERROUTER Control ROUTERROUTER Problem: Router must be fault tolerant ?

30. 30 Recovery 1. Due to the deadlock no data will be overwritten 2. Due to the deadlock no faulty data will be “stored” 3. Each FSL gate preserves its internal state  After repair the circuit resumes the operation without any additional recovery needed

31. 31 Self-healing FSL Circuits Outcome Generic approach Generic approach Ability to repair a large amount of faults Ability to repair a large amount of faults Self-healing procedure transparent for the application Self-healing procedure transparent for the applicationChallenges: Identify faulty component Identify faulty component Ensure losslessness Ensure losslessness Setup the watchdog timer Setup the watchdog timer

32. 32 Research Concept Research Concept FSL Temporal Behaviour: ARTS (Project) Selfhealing FSL Circuits (PhD) Fault Tolerance: RADIAL (Project) Basic Gates Optimization (MA) Design Flow Optimization (MA) Reference Hardware (MA)

33. 33 Temporal Behaviour : ARTS Modelling of temporal behavior is required for: Modelling of temporal behavior is required for: WCET analysis WCET analysis Communicate with other components Communicate with other components Trigger events at given points in time Trigger events at given points in time Synchronous design approach Synchronous design approach Clock provides an abstraction level Clock provides an abstraction level Clock provides a time base Clock provides a time base Application clock signal: well-defined & stable time base all calculations are based on clock periods jitter caused by hardware are masked

34. 34 Temporal Behaviour : ARTS Asynchronous design Establish a time base Establish a time base Global circuit oscillation Global circuit oscillation Reduced speed and thus limited precision Reduced speed and thus limited precision Self-Oscillating feedback loop Self-Oscillating feedback loop Synchronisation with the remaining FSL circuit Synchronisation with the remaining FSL circuit Modelling of execution time Modelling of execution time Environment (temperature, supply voltage, …) Environment (temperature, supply voltage, …) Processed data/operation Processed data/operation Circuits implementation (MUX,e.g) Circuits implementation (MUX,e.g) Application

35. 35 Temporal Behaviour : ARTS Outcome Quantitative evaluation of jitter of FSL circuits Quantitative evaluation of jitter of FSL circuits Running FSL TTP/C Controller Running FSL TTP/C ControllerChallenges: Generation of a “stable” time base Generation of a “stable” time base Parameterize the temporal behavior of FSL Parameterize the temporal behavior of FSL at gate level at gate level at circuit level at circuit level

36. 36 Conclusion FSL Current research topics: Current research topics: Design flow optimzation Design flow optimzation Reference hardware Reference hardware Efficient basic gates Efficient basic gates Fault tolerant circuits Fault tolerant circuits Self healing circuits Self healing circuits Modelling of temporal behaviour Modelling of temporal behaviour Different research fields should provide one comprehensive picture of FSL Different research fields should provide one comprehensive picture of FSL Funded master thesis available Funded master thesis available For more details see: trac.ecs.tuwien.ac.at FSL Temporal Behaviour: ARTS Selfhealing FSL Circuits Fault Tolerance: RADIAL Basic Gates Optimization Design Flow Optimization Reference Hardware