1. Performed by: Oron Port Instructor: Mony Orbach המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering Project Midterm Presentation Subject: Jitter Generator Winter 2006/7 1

2. Project Definition המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 2 Extension of the project “Jitter experiment”, performed by Gregory Zabolotov during Spring 2005 semester. Developing GUI-based software for an easy user control of the deterministic, period jitter applied on a fed clock.

3. What is Jitter? המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 5 Jitter is the short term variation of the significant instants of a digital signal from their ideal positions in time.

4. Existing Hardware & Software המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 3 Hardware: developed for the Memec 456 virtex II Pro board’s extension slot. Using a Programmable Delay Chip (PDC), it is possible to define a delay between 2.2nsec and 12.2nsec (in 10psec increments) for a given clock signal. Changing the delay continuously and periodically creates a deterministic periodic jitter effect. The JG board is connected to the SOPC’s Plb bus. The interface between the bram and the JG board was built. Software: Small program (on the SOPC) which reads a requested (via RS-232) jitter amplitude (in nsec) and frequency and loads the bram memory accordingly. Memec 456 virtex II Pro board PDC Jitter Generator (JG) PCB Extension slot

5. Project Implementation המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 5 Interface #3: Virtex II Pro’s Plb  Updating the PDC on the JG board with the current delay time, according the tables filled in the SOPC’s bram memory during interface #2. Interface already existed in prev. project. Memec 456 Board RS-232 Virtex II PRO E x t e n s i o n s l o t Jitter Gen. Data Bus Interface #1: MMI – Man-Machine-Interface GUI – Graphical-User-Interface Interface #2: RS-232 communication  Transferring a jitter period’s data selected in interface #1 to the SOPC’s bram memory, and other commands according to what was selected (start BERT, etc…)

6. Time Table המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 6 Week # DatesActionComments 1-25.11.06 - Lab introduction, initial project planning. 18.11.06 319.11.06 - Characterizing project requirements. 25.11.06 4-526.11.06 -Miluim 9.12.06 610.12.06 - Learn how to program the SOPC. Interface #2,3: Learning how previous project worked and tested. Project Characterization Presentation 16.12.06

7. Time Table המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 6 Week # DatesActionComments 717.12.06 - Interface #1: Start of GUI Creation 23.12.06 8-1024.12.06 - Interface #1: Complete. Interface #2: SOPC’s end & Computer’s software end complete. Midterm Presentation 13.01.07 11-1314.01.07 - Interface #3: Initial trial & error. Interface #3: Complete. Testing the project as a whole. 03.02.07 14- FP 04.02.07 - Finalizing documentation until final presentation, submitting files and final report. Final Presentation 06.03.07