1. EECS 700: Project Proposal TimerQueue Implementation for the HybridThread Framework Jason Agron jagron@ittc.ku.edu

2. Overview HybridThread Architecture. HybridThread Architecture. Background on “yielding” calls. Background on “yielding” calls. Timed vs. Untimed calls.Timed vs. Untimed calls. Background on nanosleep(). Background on nanosleep(). Proposed architecture. Proposed architecture. Conclusion. Conclusion. Questions. Questions.

3. HybridThread Architecture Hybrid architecture = CPU + FPGA. Hybrid architecture = CPU + FPGA. Unified programming model. Unified programming model. Threaded programming model.Threaded programming model. HW/SW co-design of OS services. HW/SW co-design of OS services. Precise, and deterministic behavior of OS components. Precise, and deterministic behavior of OS components. Good for embedded and RTOS systems.Good for embedded and RTOS systems.

4. HybridThread Architecture

5. “Yielding” System Calls Consider yield() and nanosleep() Consider yield() and nanosleep() Timed vs. Untimed  affects how a thread re-added to the R2R-Queue.Timed vs. Untimed  affects how a thread re-added to the R2R-Queue. Timed yield calls – i.e. nanosleep(). Timed yield calls – i.e. nanosleep(). Using software managed timer-queues.Using software managed timer-queues. Periodic management Periodic management Only managed at most once per system clock!Only managed at most once per system clock! Non-deterministic execution times. Non-deterministic execution times. Cache misses, branch mispredictions.Cache misses, branch mispredictions. Signal delivery, jitter due to “clock alignment”.Signal delivery, jitter due to “clock alignment”.

6. Nanosleep() POSIX specification: POSIX specification: Can sleep less than time specified.Can sleep less than time specified. Due to asynchronous signal delivery. Due to asynchronous signal delivery. Can sleep more than time specified.Can sleep more than time specified. Specified time is rounded up to resolution of system clock. Specified time is rounded up to resolution of system clock. Periodic queue management  missed timer events. Periodic queue management  missed timer events. Why is it even called NANOsleep? Why is it even called NANOsleep?

7. Proposed Solution Goal – REAL nanosecond resolution for thread sleep times w/o increased OS overhead. Goal – REAL nanosecond resolution for thread sleep times w/o increased OS overhead. Build a timer-queue IP core. Build a timer-queue IP core. HW implementation.HW implementation. Very fast, deterministic, constant queue management. Very fast, deterministic, constant queue management. Timer-events != CPU interrupts. Timer-events != CPU interrupts. HybridThread architecture allows for TQ to “talk” directly with TM and SCHED.HybridThread architecture allows for TQ to “talk” directly with TM and SCHED. Uniform interface for both SW and HW. Uniform interface for both SW and HW.

8. How it will work nanosleep(threadID,delta) nanosleep(threadID,delta) Call interacts with TimerQueue core.Call interacts with TimerQueue core. Adds an entry to a sorted queue.Adds an entry to a sorted queue. Calling thread “yields”Calling thread “yields” Time goes on  timer-events expire. Time goes on  timer-events expire. Upon expirationUpon expiration TQ sends add_thread message to the TM. TQ sends add_thread message to the TM. Single bus transaction.Single bus transaction. TQ removes timer-event entry, waits for more to expire. TQ removes timer-event entry, waits for more to expire.

9. Design Decisions Actual queue structure. Actual queue structure. Space vs. Time.Space vs. Time. Registers Registers Fast, parallel access.Fast, parallel access. Take up CLBs.Take up CLBs. BRAMs BRAMs Fast, sequential access.Fast, sequential access. Doesn’t take up CLBs.Doesn’t take up CLBs. Sorted vs. Unsorted.Sorted vs. Unsorted. “Monitor” the top of the queue vs. constant queue traversal. “Monitor” the top of the queue vs. constant queue traversal.

10. Conclusion FPGA implementation of TimerQueue FPGA implementation of TimerQueue Allows for TQ to monitor events at the rate of the FPGA clock (~100 MHz).Allows for TQ to monitor events at the rate of the FPGA clock (~100 MHz). Accurate nanosecond sleep times!!! Accurate nanosecond sleep times!!! Allows for uniform access of TQ services to both SW and HW threads!Allows for uniform access of TQ services to both SW and HW threads! Provides an abstraction of the FPGA resources for the everyday programmer!Provides an abstraction of the FPGA resources for the everyday programmer!