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DRC 2009 1 0.37 mS/ m In 0.53 Ga 0.47 As MOSFET with 5 nm channel and self-aligned epitaxial raised source/drain Uttam Singisetti*, Mark A. Wistey, Greg J. Burek, Ashish K. Baraskar, Joel Cagnon, B. J. Thibeault, S. Stemmer, A.C. Gossard, and M.J.W. Rodwell ECE and Materials Departments University of California, Santa Barbara, CA Eun Ji Kim, Byungha Shin, and Paul C McIntyre Materials Science and Engineering, Stanford University, Stanford, CA Yong-ju Lee Intel Corporation, Santa Clara, CA 2009 Device Research Conference Pennsylvania State University, State College, PA * uttam@ece.ucsb.edu
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DRC 2009 2 Outline Motivation: III-V MOSFETs Approach: Self-aligned source/drain by MBE regrowth FET and contacts Results Conclusion and future work
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DRC 2009 3 Why III-V MOSFETs Silicon MOSFETs: Gate oxide may limit <16 nm scaling IBM 45nm NMOS Narayan et al, VLSI 2006 * Enoki et al, EDL 1990 Alternative: In 0.53 Ga 0.47 As channel MOSFETs low m* (0.041 m o ) → high injection velocity (~ 2×10 7 cm/s) * → increase drive current, decreased CV/I I d / W g ~ c ox (V g -V th )v inj I d / Q transit ~ v inj / L g
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DRC 2009 4 Target device structure Target 22 nm gate length Control of short-channel effects vertical scaling 1 nm EOT: thin gate dielectric, surface-channel device 5 nm quantum well thickness <5 nm deep source / drain regions ~3 mA/ m target drive current low access resistance self-aligned, low resisitivity source / drain contacts self-aligned N+ source / drain regions with high doping
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DRC 2009 5 22 nm InGaAs MOSFET: source resistance IBM High-k Metal gate transistor Image Source:EE Times LgLg L S/D Source access resistance degrades I d and g m IC Package density : L S/D ~ L g =22 nm c must be low Need low sheet resistance in thin ~5 nm N+ layer Design targets: c ~1 m 2, sheet ~ 400
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DRC 2009 6 22nm ion implanted InGaAs MOSFET Shallow junctions ( ~ 5 nm), high (~5×10 19 cm -3 ) doping Doping abruptness ( ~ 1 nm/decade) Lateral Straggle ( ~ 5 nm) Deep junctions would lead to degraded short channel effects Key Technological Challenges
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DRC 2009 7 InGaAs MOSFET with raised source/drain by regrowth 1 Wistey, EMC 2008 2 Baraskar, EMC 2009 Interface HAADF-STEM 1* 2 nm InGaAs regrowth Self-aligned source/drain defined by MBE regrowth 1 Self-aligned in-situ Mo contacts 2 Process flow & dimensions selected for 22 nm L g design; present devices @ 200 nm gate length * TEM by J. Cagnon, Susanne Stemmer Group, UCSB
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DRC 2009 8 Regrown S/D process: key features Vertical S/D doping profile set by MBE abrupt on ~ 1 nm scale Self-aligned & low resistivity...source / drain N+ regions...source / drain metal contacts Gate-first gate dielectric formed after MBE growth uncontaminated / undamaged surface
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DRC 2009 9 Process flow* * Singisetti et al; Physica Status Solidi C, vol. 6, pp. 1394,2009
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DRC 2009 10 SiO2 W Cr FIB Cross-section Damage free channel Process scalable to sub-100 nm gate lengths Key challenge in S/D process: gate stack etch Requirement: avoid damaging semiconductor surface: Approach: Gate stack with multiple selective etches * * Singisetti et al; Physica Status Solidi C, vol. 6, pp. 1394,2009
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DRC 2009 11 Key challenge in S/D process: dielectric sidewall Sidewall must be kept thin: avoid carrier depletion, source starvation. Target < 15 nm sidewall in 22 nm L g device 20-25 nm SiN x thick sidewalls in present devices Pulse doping in the barrier: compensate for carrier depletion from D it
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DRC 2009 12 MOSFET SEMs Cross-section after regrowth, but before Mo deposition Top view of completed device Cross-section after regrowth, but before Mo deposition Top view of completed device Cross-section after regrowth, but before Mo deposition
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DRC 2009 13 MOSFET characteristics Maximum Drive current ( I d ): 0.95 mA/ m Peak transconductance ( g m ): 0.37 mS m 4.7 nm Al 2 0 3, 1×10 13 cm -2 pulse doping I d and g m below expected values
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DRC 2009 14 SEM FET source resistance InGaAs regrowth on unprocessed thin InP* Series resistance estimated by extrapolating R on to zero gate length Source access resistance ~ 500 m
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DRC 2009 15 Source resistance : regrowth TLMs W / Cr / SiO 2 gate SEM No regrowth SEM InGaAs regrowth TLMs fabricated on the regrowth far away from the gate Regrowth sheet resistance ~ 29 Mo/InGaAs contact resistance ~ 5.5 m 2 (12.6 m) TLM data does not explain 500 m observed FET source resistance FET Regrowth TLMs
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DRC 2009 16 Source resistance: electron depletion near gate Electron depletion in regrowth shadow region (R 1 ) Electron depletion in the channel under SiN x sidewalls (R 2 ) R1 R2
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DRC 2009 17 InAs source/drain regrowth 1 Wistey et al, EMC 2009 Wistey et al NAMBE 2009. 2 Bhargava et al, APL 1997 InAs regrowth Gate side of gate top of gate Mo S/D metal with N+ InAs underneath Improved InAs regrowth with low As flux for uniform filling 1 InAs less susceptible to electron depletion: Fermi pinning above E c 2
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DRC 2009 18 InAs S/D E-FET DC characteristics 4.7 nm Al 2 0 3, InAs S/D E-FET
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DRC 2009 19 Subthreshold characteristics I on /I off ~ 10 4 :1
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DRC 2009 20 Drive current and transconductance 0.95 mA/ m peak I d, ~0.45 mS/ m peak g m
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DRC 2009 21 Source-drain access resistance* R on = 600 - m for L g =0.2 m so R s < 300 m R s is too small to explain observed g m or I d *Wistey et al, NAMBE 2009
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DRC 2009 22 Self-aligned raised source/drain for scaled channel ( 5nm) D-FETs: peak I d = 0.95 mA/ m, and peak g m =0.37 mS/ m InAs Source/Drain E-FETs: peak I d = 0.95 mA/ m and peak g m = 0.45 mS/ m Next: scale to ~50 nm L g gate dielectric quality Conclusion This work was supported by Semiconductor Research Corporation under the Non-classical CMOS Research Program
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