1. Idongesit Ebong (1-1) Jenna Fu (1-2) Bowei Gai (1-3) Syed Hussain (1-4) Jonathan Lee (1-5) Design Manager: Myron Kwai Overall Project Objective: Design a chip as part of a system that accommodates the growing demand for radio frequency identification (RFID) technology while creating a quicker, more convenient shopping experience. Presentation #6: Smart Cart 525 Stage VI: 23 Feb. 2005 Component Layout and Floorplan

2. Status Design Proposal Project chosen Verilog obtained/modified Architecture Proposal Behavioral Verilog simulated Size estimates/floorplanning Gate-level implementation simulated in Verilog Floorplan and more accurate transistor count Schematic Design  Component Layout (25%)  Simulations

3. Updated Floorplan: Entire Design

4. “Layout:” Multiplier

5. Layout: Register

6. Layout: Carry-Select Adder NETLISTS MATCH!!!

7. Problems & Questions Registers  Which type to use? Current vs. NAND implementation of master-slave DFF Current: HUGE—bigger than our FA, might be even huger to make room for enable, reset, and clk signal wiring NAND: smaller, but need to AND clk with enable signal in order to perform the function we want and not sure about messing with clk