1. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Topics n State assignment. n Power optimization of sequential machines. n Design validation. n Sequential testing.

2. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR State assignment n Encoding bits in symbolic state = state assignment. n State assignment affects: –combinational logic area; –combinational logic delay; –memory element area.

3. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR State assignment in n-space

4. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR State assignment and delay

5. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Power optimization Memory elements stop glitch propagation:

6. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Sequential testing n Much harder than combinational testing - can’t set memory element values directly. n Must apply sequences to put machine in proper state for test, be able to observe value of test.

7. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Example

8. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Testing the machine n To test NOR for stuck-at-1, must set both NOR inputs to 0. n Primary input i1 can be controlled directly. n To set lower NOR input, must set state to ps0 = ps1 = 0.

9. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Example state machine State codes: s0 = 11 s1 = 10 s2 = 01 s3 = 00

10. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Controlling an FSM n Don’t know initial state of machine. n Must find a sequence which drives machine to required state independent of initial state. n State sequence for test: * -> s0 -> s1 -> s3.

11. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Time-frame expansion n A model for sequential test: unroll machine in time. n Time frame expansion illustrates how single-stuck-at fault in sequential machine appears to be multiple-SA fault.

12. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Time-frame expansion example

13. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR

14. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Unreachable states n State assignment may cause some states to be unreachable. n As a result, it may not be possible to apply some required test values.

15. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Unreachable state example

16. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Example n State codes: –s0 = 00 –s1 = 01 –s2 = 10. n This creates a fourth state which is unreachable.

17. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Implemented FSM

18. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR

19. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR LSSD n LSSD = level-sensitive scan design. n Way to achieve full controllability, observability of registers. n Links all registers in a scan chain.

20. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR LSSD latch

21. Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Partial scan n Full scan is expensive - must roll out and roll in state many times during a set of tests. n Partial scan selects some registers for scanability. n Requires analysis to choose which registers are best for scan.