1. Evaluation of Redundancy Analysis Algorithms for Repairable Embedded Memories by Simulation Laboratory for Reliable Computing (LaRC) Electrical Engineering Department National Tsing Hua University Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, and Cheng-Wen Wu

2. 2 Outline  Introduction  RA Algorithm Evaluation by Simulation  Simulation Time Reduction  RA Design Verification  Experimental Results  Conclusions

3. 3 Introduction  Memory cores dominate the SOC silicon area  Density of memory circuit and layout is much higher than logic  Yield of memory cores thus dominates yield of the SOC  Improving the yield of the memory cores is an increasingly important issue  Effective built-in redundancy-analysis and self- repair methodologies need to be developed

4. 4 Chip Area Breakdown Source: International Technology Roadmap for Semiconductors (ITRS), 2000

5. 5 Memory BISR Design  What and how to design memory BISR?  Memory spec  Yield analysis  Redundancy analysis algorithm develop  Repair rate evaluation  Spare elements selection  BISR design  Verification

6. 6 Redundancy Analysis  RA algorithm is the main factor affecting repair efficiency Faulty Memory Method 1: Row first Can not repair Method 2: Column first Can not repair Method 3: Greedy Can be repaired RA is important

7. 7 RA Simulation and Verification

8. 8 Memory Specification File # Memory Configuration Oriented = 1 # word-oriented or bit-oriented Word_Length = 16 Block_Size = 256x16 Block_Count = 4 #Redundancy Design Spare_Rows = 2 Spare_Columns = 8 # Defects and Faults Prob. Random_Defects = 20 Faulty_Rows = 15 Faulty_Columns = 10 Cluster_Faults = 5 # Test Algorithms March=

9. 9 Defect Injection  Only point defects are assumed (no bulk defects)  Defect count distributions:  Poisson, Gamma, Negative binomial, etc.  Defect locations:  Randomly distributed on wafer/die  Defect distribution is process dependent

10. 10 Fault Translation  Defects lead to:  Faulty address decoder  Faulty sense amplifier  Faulty cells due to, e.g., coupling between bit- lines/word-lines  Defects are translated to:  Single cell fault  Faulty row  Faulty column  Cluster fault  Etc.  User can set the probability of each fault type

11. 11 Test Algorithm Simulation  Fault information collected on-line  Each Read operation provides different information  Each fault can be detected by different Read operation  BISR is an on-the-fly repair scheme  The fault detection of test algorithm should be considered at RA simulation

12. 12 Example: March C– Test FaultR1R1 R2R2 R3R3 R4R4 R5R5 R1R1 R2R2 R3R3 R4R4 R5R5 SAF(0).1.1. SAF(1) 0.0.0 TF(U).1.1. TF(D)..0.0 CF in (D;~)<.1..0 CF in (D;~)>..01. CF in (U;~)< 0..1. CF in (U;~)>.10.. CF st (0;0)<.1... CF st (0;0)>...1. CF st (0;1)<..0.0 CF st (0;1)> 0...0

13. 13 Redundancy Analysis  Our RA simulator evaluates different RA algorithms and report the respective repair rates and area overheads  The RA algorithms are provided by the user  Using function calls  Spare element types:  Row, column, word, bit, etc  Global/local  Shared/non-shared

14. 14 Repair Rate Evaluation   3-D plot for repair rate

15. 15 Yield and Repair Rate  Notations  Y: total yieldA: main memory area  A r : redundant memory area  A c : logic circuit of BISR area  d m : defect density of memory cores  d c : defect density of logic cores  RR: repair rate  Yield can be derived from repair rate

16. 16 Graphical User Interface

17. 17 Simulation Time Reduction  Criterion 1: N ⊕ N sr + N sc  can’t repair  Criterion 2: N sr + N sc – N fr – N fc N sfc  repairable A faulty memory with N ⊕ = 8 N ⊕ : orthogonal cell count N sr : spare row count N sc : spare column count N fr : faulty row count N fc : faulty column count N sfc : single faulty cell count

18. 18 RA Design Verification  During BISR design, the verification is harder  BISR includes BISD, BIRA, and Address Reconfiguration circuit  Verification of each part can be done, but the whole BISR verification can not be done easily  The pattern for BISR verification is diversified fault bit maps  The simulator also can generate many diversification fault bit maps

19. 19 Verification Flow

20. 20 Bit-Oriented Memory Example  Size: 2048x55  Single block  Defects: 1-20 (Poisson distribution)  Faulty rows: 15%  Single faulty cells: 85%  Spare rows: 1-10  Spare columns: 1-10

21. 21 Experimental Result RCRRAreaRCRRArea 1875.26%164396482.12%8522 7275.52%44814682.20%12508 9175.61%25433782.55%14501 2775.78%144465582.81%10515 3675.87%124539285.24%4591 4576.13%1046011085.76%20535 5476.74%84672986.55%18542 6376.91%64745686.98%12563 10178.12%25983887.29%16549 1981.15%184874787.33%14556 8281.34%45368387.41%6584 2881.51%164947487.67%8577 7381.67%65296587.67%10570 Target repair rate: 75% Area overhead is less than 5000 cells

22. 22 Word-Oriented BISR  Memory size: 8K x 64 (8K x 32 x 2)  Spare element (generate by memory compiler)  4 spare row  2 spare column group (4 column/group)  RA algorithm split column in to 4 segments  BISR gate count: 5.6K  Hardware overhead of spare element: 4.57%  Hardware overhead of BISR: 4.6% Source: “A built-in self-repair scheme for semiconductor memories with 2-D redundancy”, ITC 2003.

23. 23 RR with Different Group Size

24. 24 Test Chip

25. 25 Conclusions  We developed a simulator for evaluating the embedded-memory repair rates under different  Redundancy analysis algorithms  Spare-element configurations  It helps evaluate built-in redundancy-analysis algorithms and develop self-repair schemes  It also helps BISR design verification  It is fast and effective