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VHDL AES 128 Encryption/Decryption

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Presentation on theme: "VHDL AES 128 Encryption/Decryption"— Presentation transcript:

1 VHDL AES 128 Encryption/Decryption
Bradley University Department of Electrical and Computer Engineering Senior Capstone Project Advisor: Dr. Vinod Prasad David Leifker Gentre Graham April 7th 2005

2 Presentation Outline Project Introduction Functional Description
Difficulties & Solutions Simulation, Verification, & Demonstration Conclusion

3 Project Introduction: AES
AES (Advanced Encryption Standard) Key Lengths 128,192,256 bits (FIPS 197) Block Cipher Approved by NSA (National Security Agency) Plain Text Unencrypted Data Cipher Text Encrypted Data Encryption Key (Secret Key) Enables conversion between Cipher Text & Plain Text

4 Project Introduction VHDL (Very High Speed Integrated Circuit Hardware Description Language) FPGA (Field-Programmable Gate Array) HID ( Human Interface Device) PS/2 Keyboard LCD ( Liquid Crystal Display )

5 Project Introduction: Applications
Secure Communication ATM DVD Content Secure Networks Secure Storage Confidential Corporate Documents Government Documents FBI Files Personal Storage Devices Person Information Protection

6 Project Introduction: Hardware
PC with Xilinx ISE 6.31i NU Horizons Xilinx Spartan III Development Board XCS400-4 PQ208C PS/2 Input 4 x 20 Line LCD Display

7 Presentation Outline Functional Description Project Introduction
Difficulties & Solutions Simulation, Verification, & Demonstration Conclusion

8 Functional Description

9 Sub-System Block Diagram
Program Control Logic PS2 Keyboard Interface AES Core 719 LoC 180 LoC RAM 51 LoC 1254 LoC LCD Interface ROM Misc. LoC: 290 440 LoC 67 LoC Total Lines of Code ≈ 3000

10 Sub-System Block Diagram

11 Inside The AES Core Key Expansion Encryption Decryption MixColumns
Inverse MixColumns Rcon Shift Rows Inverse Shift Rows Substitute Byte Inverse Substitute Byte Add Round Key

12 Inside The AES Core Current State Key Schedule Next State
Add Round Key

13 Substitute Byte & Inverse
Inside The AES Core Current State Next State 256 Byte Array Substitute Byte & Inverse

14 Inside The AES Core Next State Current State Shift Rows & Inverse

15 Inside The AES Core Current State Next State MixColumns

16 Inside The AES Core Next State Current State Inverse MixColumns

17 Presentation Outline Difficulties & Solutions Project Introduction
Functional Description Difficulties & Solutions Simulation, Verification, & Demonstration Conclusion

18 Difficulties & Solutions
Development Board PS/2 Port Replaced with External PS/2 Port Development Board Documentation Did Not Reflect Board Specifications Clock Speed LCD Character Addressing (4x24 vs 4x20) LCD Timing Test Bench Development Area Constraints of the FPGA Hard Coded Encryption Key Reduction of States by Looping (LCD)

19 Presentation Outline Simulation, Verification, & Demonstration
FIPS 197 Documented Example ModelSim Computer Simulation FPGA Demonstration

20 Demonstration: FIPS 197

21 Demonstration: Encryption

22 Demonstration: Decryption

23 Demonstration: Encryption
ModelSim Computer Simulation

24 Demonstration: Decryption
ModelSim Computer Simulation

25 Software Flow Chart

26 Demonstration: Splash Screen

27 Demonstration: ASCII Input

28 Demonstration: ASCII Input

29 Demonstration: ASCII Input

30 Demonstration: HEX Input

31 Demonstration: Encryption

32 Demonstration: Decryption

33 Improvements & Additions
Larger LCD Display 192 or 256 Bit level Encryption High Speed Mode PC Integration

34 Questions?

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