1. August 12 2008SGSS front end, Summary August 2008 Edwin Spencer, SCIPP1 SGST Preview SCIPP, UC Santa Cruz Andrey Martchovsky Gregory Horn Edwin Spencer SGST: SiGe Silicon Tracker front end IC

2. August 12 2008SGSS front end, Summary August 2008 Edwin Spencer, SCIPP2 Architecture of front end channel: preamp and diffamp 118uA 7u 2.4u 11.4u 3.2u 3.2u SGST biases total: 168 uA @ 16.2 pF, 108 uA @ 5.5 pF(900 e-) POWER: 0.202 mW/channel @ 16.2 pF, VT=1fC and 0.130 mW @ 5.5 pF, VT=0.5 fC

3. August 12 2008SGSS front end, Summary August 2008 Edwin Spencer, SCIPP3 Shaper schematic 8u 2u 3u

4. August 12 2008SGSS front end, Summary August 2008 Edwin Spencer, SCIPP4 Comparator Schematic 10u (digital)

5. August 12 2008SGSS front end, Summary August 2008 Edwin Spencer, SCIPP5 SGST Overview IBM 8WL process, 0.13  m 8RF CMOS with SiGe 140 Ghz npn added. Submitted using IBM Cadence kit to MOSIS on June 30, 2008. Circuit development goal: meet SCT 25 ns crossing specs where practical for power minimization. The prototype circuit should be testable for SiGe 8WL radiation evaluation. Two detector loads simulated, including strays, of 5.5 pF for VT= 1fC and 16 pF for VT = 0.5 fC. This corresponds to 2.5 cm and 10 cm sensor strip length. Linear regulator included, input 1.4 V, output is 1.2 V for channel. Bias adjustment for threshold matching skew included, using different strategy than ABCD for lowered power rail. Resistive front transistor feedback used to reduce npn base shot noise. Control voltage VSHAPE used to adjust shaping time, +/- 15 % range.

6. August 12 2008SGSS front end, Summary August 2008 Edwin Spencer, SCIPP6 SGST Simulated ENC performance 600 nA detector leakage is included. 1350 e- @ 16.2 pF

7. August 12 2008SGSS front end, Summary August 2008 Edwin Spencer, SCIPP7 Impulse Response at Comparator 5.5 pF I front = 100uA, 110uA 16.2 pf I front = 170uA, 180 uA, 200 uA 27ns impulse response

8. August 12 2008SGSS front end, Summary August 2008 Edwin Spencer, SCIPP8 AC simulation-phase margin 16.2 pF@120  A 0dB@42Mhz, 57.3° margin 72 degrees phase margin

9. August 12 2008SGSS front end, Summary August 2008 Edwin Spencer, SCIPP9 AC simulation-phase margin 16.2 pF @ 150  A 0 dB@26 Mhz, 66° margin 70 degrees @ 150  A

10. August 12 2008SGSS front end, Summary August 2008 Edwin Spencer, SCIPP10 Transient simulation conditions Nominal bias condition Detector capacitance default is 16.2 pF, unless otherwise noted Charge collection time is 10 ns No parasitic extraction included

11. August 12 2008SGSS front end, Summary August 2008 Edwin Spencer, SCIPP11 Diffamp and Shaper Out: 1, 2.8, 4.6, 6.4, 8.2, 10 fC

12. August 12 2008SGSS front end, Summary August 2008 Edwin Spencer, SCIPP12 Comparator output: Time Walk (TW) TW (10 – 1.25 fC) =11.9 ns, TW( 10 – 1.02fC) = 17.5 ns 15.4 ns for 10fC – 1.25 fC span

13. August 12 2008SGSS front end, Summary August 2008 Edwin Spencer, SCIPP13 Preamp Input impedance for 120  A bias At 30 Mhz, 322 Ω for 180 uA, 464 Ω for 106 uA 220 ohms @ 30 Mhz

14. August 12 2008SGSS front end, Summary August 2008 Edwin Spencer, SCIPP14 Preamp Input impedance for 150  A bias At 30 Mhz, 322 Ω for 180 uA, 464 Ω for 106 uA Drops to 200 ohms with increase of front bias by 25 %

15. August 12 2008SGSS front end, Summary August 2008 Edwin Spencer, SCIPP15 PSRR AC simulation of 3 stages -18 dB PSRR (power supply rejection ratio) for shaper_out without regulator filter. Overall PSRR -7 dB, improved by front cascode

16. August 12 2008SGSS front end, Summary August 2008 Edwin Spencer, SCIPP16 Process Monte Carlo: 150  A bias, 16.2 pf load VSHAPE= 600 mV Monte Carlo shows guassian process variation, so no bias issues for sample of 500 runs. Final shape is 30.9 ns +/- 2.1 ns.

17. August 12 2008SGSS front end, Summary August 2008 Edwin Spencer, SCIPP17 Process Monte Carlo: 150  A bias, 16.2 pf load VNcap feedback, VSHAPE= 200 mV For high setting of VSHAPE, peaking time is 28.8 ns, +/- 2.1. SNR is clustered well.

18. August 12 2008SGSS front end, Summary August 2008 Edwin Spencer, SCIPP18 Process Monte Carlo: 150  A bias, 16.2 pf load VNcap feedback, VSHAPE= 1200 mV For lowest VSHAPE setting, peak is 21.3 ns.

19. August 12 2008SGSS front end, Summary August 2008 Edwin Spencer, SCIPP19 Process Monte Carlo: 150  A bias, 16.2 pf load MIMcap feedback, VSHAPE= 200 mV Sigma on shape goes to 1.8 ns (from 2.1), a useful improvement by changing feedback cap technology.

20. August 12 2008SGSS front end, Summary August 2008 Edwin Spencer, SCIPP20 Process Monte Carlo: 150  A bias, 16.2 pf load MIMcap feedback, VSHAPE= 1200 mV

21. August 12 2008SGSS front end, Summary August 2008 Edwin Spencer, SCIPP21 SGST progress status COMPLETED IBM 8WL kit functionality, DRC and LVS and monte carlo. Channel and bias, simulated with most monte carlo checks done. Channel laid out on 30 um pitch assembly packing checked. Linear regulator simulated with monte carlo. NEEDED Final monte carlo of channel and bias. Bias circuit layout. Padframe and protection layout. Simple serial digital readout design (IBM 8RF digital library in kit and will not need modification). LVDS driver design and layout. Submit for MOSIS October 20 th 8WL run