1. Decoders Module M9.1 Section 6.3

2. Decoders TTL Decoders

3. Decoders A B Y0 Y1 Y2 Y3 2-to-4 Decoder 0 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 1 0 1 1 1 0 0 0 1 0 1 1 0 1 1 1 0 0 0 1 1 1 1 0 B A Y0 Y1 Y2 Y3 !Y0 !Y1 !Y2 !Y3 A decoder with N inputs has 2 N outputs

4. Decoders 0 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 1 0 1 1 1 0 0 0 1 0 1 1 0 1 1 1 0 0 0 1 1 1 1 0 B A Y0 Y1 Y2 Y3 !Y0 !Y1 !Y2 !Y3 Y0 = !B & !A Y1 = !B & A Y2 = B & !A Y3 = B & A Define pins for active low outputs: ![Y3..Y0] PIN 39,37,36,35 ISTYPE 'com';

5. 24decode.abl MODULE Decoder24 TITLE '2 to 4 Decoder, A. Student, 7/15/02' DECLARATIONS " INPUT PINS " B PIN 6; " Switch 1 A PIN 7;" Switch 2 " OUTPUT PINS " Y3..Y0 PIN 39,37,36,35 ISTYPE 'com';" LED 5..8 EQUATIONS Y0 = !B & !A; Y1 = !B & A; Y2 = B & !A; Y3 = B & A; END Decoder24 0 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 1 0 1 1 1 0 0 0 1 0 1 1 0 1 1 1 0 0 0 1 1 1 1 0 B A Y0 Y1 Y2 Y3 !Y0 !Y1 !Y2 !Y3

6. 24decode.abl MODULE Decoder24 TITLE '2 to 4 Decoder, A. Student, 7/15/02' DECLARATIONS " INPUT PINS " B PIN 6; " Switch 1 A PIN 7;" Switch 2 " OUTPUT PINS “ " LED 5..8 active low ![Y3..Y0] PIN 39,37,36,35 ISTYPE 'com'; EQUATIONS Y0 = !B & !A; Y1 = !B & A; Y2 = B & !A; Y3 = B & A; END Decoder24 0 0 1 0 0 0 0 1 1 1 0 1 0 1 0 0 1 0 1 1 1 0 0 0 1 0 1 1 0 1 1 1 0 0 0 1 1 1 1 0 B A Y0 Y1 Y2 Y3 !Y0 !Y1 !Y2 !Y3 Active Low

7. 3-to-8 Decoder C B A !Y0 !Y1 !Y2 !Y3 !Y4 !Y5 !Y6 !Y7 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1 0 1 1 1 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0

8. 38decode.abl MODULE Decoder38 TITLE '3 to 8 Decoder, A. Student, 7/15/02' DECLARATIONS " INPUT PINS " C PIN 6;" Switch 1 B PIN 7; " Switch 2 A PIN 11;" Switch 3 " OUTPUT PINS " ![Y7..Y0] PIN 44,43,41,40,39,37,36,35 ISTYPE 'com'; " LED 1..8

9. 38decode.abl (cont’d) EQUATIONS Y0 = !C & !B & !A; Y1 = !C & !B & A; Y2 = !C & B & !A; Y3 = !C & B & A; Y4 = C & !B & !A; Y5 = C & !B & A; Y6 = C & B & !A; Y7 = C & B & A; END Decoder38 C B A !Y0 !Y1 !Y2 !Y3 !Y4 !Y5 !Y6 !Y7 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1 0 1 1 1 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 Recall: " OUTPUT PINS " ![Y7..Y0] PIN 44,43,41,40,39,37,36,35 ISTYPE 'com'; Active Low

10. Full Adder 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 C i A i B i S i C i+1 11 11 CiCi AiBiAiBi 00011110 0 1 SiSi

11. Implementing a Binary Adder Using a Decoder S(X,Y,Z) =  m(1,2,4,7) C(X,Y,Z) =  m(3,5,6,7)

12. TTL Decoders 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 GND Vcc1G 1A 1B 1Y0 1Y1 1Y2 1Y3 2G 2A 2B 2Y0 2Y1 2Y2 2Y3 74LS139 Y0 Y1 Y2 Y3BA G 1 X X 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 1 1 0 1 0 1 1 0 1 0 1 1 1 1 1 0 Dual 2-4 Decoder

13. TTL Decoders 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 GND VccA B C G1 Y7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 !G2A !G2B 74LS138 ABC Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 G1 G2 G2 = G2A # G2B X = don't care X 1 X X X 1 1 1 1 1 1 1 1 0 X X X X 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 0 1 1 1 1 1 1 1 0 0 1 0 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 1 1 0 1 0 0 1 1 1 1 0 1 1 1 1 0 1 0 1 1 1 1 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 0 3-to-8 Decoder

14. Recall: TTL Demultiplexer 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 GND Vcc1C 1G B 1Y3 1Y2 1Y1 1Y0 2C 2G A 2Y3 2Y2 2Y1 2Y0 74LS155 1 X X X 1 1 1 1 0 1 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 1 0 X 0 X X 1 1 1 1 G C B A Y0 Y1 Y2 Y3 X = don’t care Dual 1-to-4-line demultiplexer