1. Performance Analysis of Processor Characterization Presentation Performed by : Winter 2005 Alexei Iolin Alexander Faingersh 307724211 Instructor: 306966912 Evgeny Fiksman

2. Agenda Introduction & Project Goals Introduction to Xilinx EDK and MicroBlaze® System block diagram Schedule

3. General In the past few years there is an increasing activity in using Soft core Processors implemented on FPGA’s and embedded systems MicroBlaze is a Soft core Processor developed by Xilinx that meets performance, area-efficiency and low cost targets Although using the MicroBlaze enables fast system development on a single FPGA, some of the “special” applications run slower than in Hardware IP

4. Project Goals Examination of MicroBlaze calculation abilities by measuring the time and the power consumption of running application. Using as application code one of well known benchmarks. Such as: DHRYSTONE MIPS,SPEC CPU 2000. Adding self written C code for testing FPU. Such as: FFT, DCT. Exporting SW arbitrary block to Hardware and using it as a hardware accelerator for MicroBlaze.

5. EDK and MicroBlaze The Embedded Development Kit (EDK) is a set of microprocessor design tool and common software platforms. The EDK includes the Platform Studio tool suite, the MicroBlaze core and a library of peripheral IP cores. The MicroBlaze embedded soft core is a 32-bit Reduced Instruction Set Computer (RISC) optimized for implementation in FPGA. Operating at up to 200 MHz. MicroBlaze enables you to have complete flexibility in setting peripherals, memory and interface features on a single FPGA

6. Hardware FG456 SW Reset 1.5v Power supply block for VERTEX core Special jumper allow current measurement

7. Time & power consumption measurement technique For time measurement we will use FPGA’s OPB peripheral's devices such as: OPB Timer/Counter and OPB Interrupt controller. For current measurement we will use power resistor and external DAC such as: Digital signal recorder in Oscilloscope and NI DAC (Labveiw) External DAC Power resistor

8. System block diagram OPB Timer/Controller Hardware Accelerator

9. Time Table EDK trainings Studying the communication with OPB Timer and Controller Measuring execution time for basic application files. Studying the Dhrystone Benchmark specification and adding self written block for FPU examination Midterm presentation Implementation of arbitrary SW block in HW for hardware acceleration Performance & Power consumption measurements DONE 3 WEEKS 1 WEEK 4 WEEKS

10. Questions?