ST7 MICROCONTROLLER TRAINING

ST7 MICROCONTROLLER TRAINING
1 - INTRODUCTION 2 - CORE 3 - ADRESSING MODES 4 - PERIPHERALS 5 - ST7 SOFTWARE TOOLS 6 - ST7 HARDWARE TOOLS 7 - STVD7 ST7 PERIPHERALS

ST7 I/O PORTS Optional features : Optional AD converter 16-bit Timer
8-bit Auto Reload Timer SPI SCI I2C EEPROM Programmable OpAmp CAN Optional ST623x BLOCK DIAGRAM Peripheral PORT 16-bit timer Power Supply Watchdog Timer Data Ram 256 bytes Oscillator Reset Test/Vpp INT Program Otp / Rom Interrupt Controller 8-Bit CORE SP PCH Accu Index X Index Y CC Data EEprom PCL ST7 PERIPHERALS

ST7 I/O PORTS Overview ALL THE I/Os ARE INDIVIDUALLY SOFTWARE CONFIGURABLE USING 3 DIFFERENT REGISTERS : DDR: Data Direction Register DR: Data Register OR: Option Register ST72254 : 22 MULTIFUNCTION BIDIRECTIONAL I/O LINES 18 Standard I/Os (sink up to 5mA) 8 High Current I/Os (PA0-PA7 can sink up to 20mA) 6 Analog Inputs (PC0-PC5) 16 alternate Functions on 16 pins (for Timers, SPI and I2C) All the I/Os can be set-up as Interrupt inputs ST7 PERIPHERALS

ST7 I/O PORT Safe I/O pin transition
DDR OR Mode Floating input 1 Input pull- up with/without interrupt Output Open-Drain Output Push-Pull 01 00 10 11 Reset State ST7 PERIPHERALS

ST7 I/O PORT Basic structure
Read / Write DDRi Data Direction Register Bit Write DRi Latch Data Output bit I/O Pin Ouput Input Reg bit Read DRi Input I/O SOFTWARE SELECTABLE CONFIGURATION HIGH FLEXIBILITY for software and PC board layout ST7 PERIPHERALS

ST7 I/O PORT Settings & electrical behaviour
Configuration given when no external Hardware is connected the pins Input Floating Input Pull_up Ouput Open Drain Ouput Push-Pull DDR 1 OR Written DR I/O Pin Floating Vdd Vss Read DR X ST7 PERIPHERALS

ST7 EXTERNAL INTERRUPTS
Pin 1 Interrupt Source 1 ST7 Interrupt Controller Pin 2 Edge/level selection Pin M Pin 1 Interrupt Source 2 Pin 2 Edge/level selection Pin N Miscellaneous Register Pin 1 Interrupt generation Pin 2 Interrupt source Negative edge only Latched Positive edge only Latched Negative edge and low level Not Latched Positive and Negative edge Latched ST7 PERIPHERALS

ST7 I/O PORT Block Diagram
REGISTER ACCESS Output Stage ALTERNATE OUTPUT V DD 1 ALTERNATE ENABLE DR DDR PULL-UP PAD OR Condition DATA BUS OR SEL DDR SEL CMOS SCHMITT TRIGGER DR SEL 1 ANALOG INPUT ALTERNATE INPUT EXTERNAL INTERRUPT SOURCE FROM OTHER BITS POLARITY SELECTION Input Stage ST7 PERIPHERALS

PROGRAMMING TIPS I/O Port (1)
AD CONVERTION Each pin used by the ADC cell must be configured as floating input (i.e. without pull-up resistors) before activating the analog input mode ALTERNATE FUNCTION A signal coming from an on-chip peripheral can be output on a port. In this case, the I/O is automatically configured in output mode. A signal coming from an I/O can be an input to an on-chip peripheral. In this case, it must be configured as Input without interrupt (Floating Input). ST7 PERIPHERALS

PROGRAMMING TIPS I/O Port (2)
Open Drain Outputs can be used for bus driving where several devices are connected on the same line. They can be wired together to increase current drive capability Voltages driving an Analog Input should always stay within the absolute maximum ratings (Vss-0.3V to Vdd+0.3V) Pull-up resistors typically deliver 50µA under 5V The toggling time on any output pin will be approximately 30ns for a 50pF load ST7 PERIPHERALS

I/O Ports Configuration Example
Fill the dedicated I/O port registers in order to have the following configuration: PB0:PB2 Push-Pull Output (high level) PB3,PB4 Floating Input PB5 Input with Interrupt PB6 Push-Pull Output (low level) PB7 Ouput (High Impedance) PBDR7 PBDR0 PBDR PBDDR7 PBDDR0 PBDDR PBOR7 PBOR0 PBOR ST7 PERIPHERALS

A/D CONVERTER Optional features : AD converter 16-bit Timer

ST7 AD CONVERTER Overview (1)
8-BIT SUCCESSIVE APPROXIMATIONS CONVERTER WITH UP TO 8 ANALOG CHANNELS: ST72254 : 6 inputs ST72334 and ST725xx : 8 inputs ST72171 : 6 external inputs + 2 internal inputs FEATURE : Accuracy : 1 LSB Total Unajusted Error MAX : 1 LSB Conversion time : 24 CPU cycle ie 3µs at full speed (8MHz) FLAGS COCO : end of conversion (Status flag) ADON : ADC on/off bit (to reduce power consumption) ST7 PERIPHERALS

ST7 AD CONVERTER Overview (2)
LOW CONSUMPTION MODES Wait mode doesn't affect the ADC Halt mode stops the ADC. HARDWARE ST72334 and ST725xx : Vdda and Vssa must be connected externally respectivelly to Vdd and Vss through decoupling capacitors. ST72254 : connection done internally RATIONETRIC In the Functionnal Range If analog voltage input > Vdd : converted result = FFh (no overflow indication) If analog voltage input < Vss : converted result = 00h (no underflow indication) ST7 PERIPHERALS

ST7 AD CONVERTER Block diagram
COCO - ADON - CH2 CH1 CH0 (Control Status Register) CSR AIN0 AIN1 AIN2 SAMPLE AIN3 ANALOG & ANALOG TO AIN4 MUX HOLD DIGITAL AIN5 CONVERTER AIN6 AIN7 Fcpu AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 (Data Register) DR ST7 PERIPHERALS

PROGRAMMING TIPS AD Converter
PROCEDURE Step 1 : The analog input pins must be set-up as Input no pull-up no interrupt Step 3 : assign a channel for the conversion (bit CH0, CH1 and CH2 in CSR register) and set the ADON bit Step 4 : Wait until COCO bit set. A continuous conversion is performed. To reach the best accuracy, the impedance seen by the analog input pin must be lower than 10Kohm. Beginning of a new conversion by writing in the CSR (select the analog channel) Continuous ADC Write in CSR : ® Stop conversion If ADON still set : new conversion Else stop ADC ADC init : IO config Channel selected ADON bit set t = 3µs ST7 PERIPHERALS

ADC Configuration Example
Fill ADCCSR register in order to have an analog conversion on AIN4. What bit has to be tested to know the end of the conversion ? COCO ADON CH3 CH2 CH1 CH0 ADCDR ST7 PERIPHERALS

ST7 16-bit TIMER Optional features : 16-bit Timer AD converter

16-bit TIMER Overview (1) 16-bit free running counter driven by a software configurable prescaler 4 different modes : Input capture (2 pins) : to latch the value of the counter after a transition on the ICAPi pin Output compares (2 pins) : to control an output waveform or to indicate when a period of time is over One pulse : generation of a pulse when an external event occurs PWM : generation of a signal with frequency and pulse length set by software (OCR1 and OCR2) ST7 PERIPHERALS

16-bit TIMER Overview (2) The timer clock can be provided by :
The internal clock with a configurable ratio An external source : Fext must 4 times slower than the internal clock (ie Fmax=2Mhz) CC1 CC0 Timer clock Fcpu/4 1 Fcpu/2 Fcpu/8 External ST7 PERIPHERALS

16-bit TIMER Block diagram
ST7 INTERNAL BUS MCU-PERIPHERAL INTERFACE CPU CLOCK 8 LOW BYTE 8-BIT BUFFER EXEDG HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE HIGH BYTE LOW BYTE 1/2 1/4 1/8 16-BIT FREE RUNNING COUNTER OUTPUT COMPARE REGISTER 1 REGISTER 2 INPUT CAPTURE COUNTER ALTERNATE REGISTER EXCLK 16 16 16 CC1 CC0 EDGE DETECT CIRCUIT 2 16-Bit INTERNAL TIMER BUS ICAP1 OUTPUT COMPARE CIRCUIT OVERFLOW DETECT CIRCUIT EDGE DETECT CIRCUIT 1 ICAP2 LATCH 1 OCMP1 STATUS REGISTER ICF1 OCF1 TOF OCF2 ICF2 LATCH 2 OCMP2 ICIE OCIE TOIE IEDG1 OLVL2 FOLV1 FOLV2 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG CONTROL REGISTER 1 CONTROL REGISTER 2 TIMER INTERNAL INTERRUPT ST7 PERIPHERALS

16-bit TIMER Input capture (1)
Captures the counter value upon input signal edge detection Allows an external pulse length measurement Internal safety process in case of critical interrupts timing Timer Counter Register Edge Detector Input Capture Register ICAP1A Software Maskable Interrupt Request ST7 PERIPHERALS

16-bit TIMER Input capture (1)
ICAP1 (Control Register 1) CR1 EDGE DETECT EDGE DETECT ICAP2 ICIE IEDG1 CIRCUIT2 CIRCUIT1 (Status Register) SR IC2R IC1R ICF1 ICF2 (Control Register 2) CR2 16-BIT 16-BIT FREE RUNNING CC1 CC0 IEDG2 COUNTER ST7 PERIPHERALS

16-bit TIMER Ouput compare (1)
Event generation (Interrupt request/bit toggling) whenever the compare register matches the counter Indicates a period of time has elapsed and controls an output waveform Internal safety process in case of critical interrupts timing Timer Counter Register Software Maskable Interrupt Request Pulse generation Match? Output Compare Register ST7 PERIPHERALS

16-bit TIMER Output compare (2)
FREE RUNNING OC1E OC2E CC1 CC0 COUNTER (Control Register 2) CR2 16-bit (Control Register 1) CR1 OUTPUT COMPARE Latch OCIE OLVL2 OLVL1 CIRCUIT OCMP1 1 Latch OCMP2 2 16-bit 16-bit OC1R OC2R OCF1 OCF2 (Status Register) SR ST7 PERIPHERALS

16-bit TIMER Real Time Clock
In each Interrupt Routine the OCR Register content is updated. There is no shift time (the counter is never reset externally). FREE RUNNING COUNTER VALUE FFFFh OCR+DT OCR 0000h Timer IT Timer IT time ST7 PERIPHERALS

16-bit TIMER One pulse mode (1)
Generation of a pulse synchronized with an external event Allows Phase Locked Loop Generation On Input Capture event The counter is reset The timer output pin is toggled On Output compare event The timer waits for the next Input Capture event ST7 PERIPHERALS

Free running counter is initialized to FFFCh OLVL2 bit level is applied on the OCMP1 pin I CF1 bit is set When a external event occurs on ICAP1 pin When the free running counter reaches OC1R register value OLVL1 bit level is applied on the OCMP1 pin ST7 PERIPHERALS

FREE RUNNING COUNTER VALUE FFFFh FFFCh Compare 1 0000h time ICAP1 Input Capture pin Timer input time OCMP1 Ouput Compare pin Timer output time ST7 PERIPHERALS

16-bit TIMER PWM mode (1) Automatic generation of a Pulse Width Modulated signal Period &pulse lenght set by software: The first Output Compare Register OC1R contains the length of the pulse The second Output Compare Register OCR2 contains the period of the pulse Resolution up to 100 steps at 20 KHz (fCPU =4 MHz): 1% of accuracy on the duty cycle ST7 PERIPHERALS

ST7 TIMER PWM mode (2) Free running counter is initialized to FFFCh
OLVL2 bit level is applied on the OCMP1 pin ICF1 bit is set When the free running counter reaches OC2R register value When the free running counter reaches OC1R register value OLVL1 bit level is applied on the OCMP1 pin ST7 PERIPHERALS

ST7 TIMER PWM mode (3) Tmax = Ttimer × 65535 OLVL2= 1 OLVL1=0 FFFFh
FREE RUNNING COUNTER VALUE Tmax = Ttimer × 65535 FFFFh FFFCh Compare 2 Compare 1 0000h time OCMP1 Ouput Compare pin Timer output OLVL2= 1 OLVL1=0 time ST7 PERIPHERALS

PROGRAMMING TIPS 16-bit timer (1)
Define Input capture pins as inputs through the corresponding Data Direction Register Read MSB first and then the LSB The counter LSB is buffered during the MSB read The counter LSB read accesses the buffered value Any access to the high byte disables the corresponding timer function until the low byte is accessed Disable the interrupts during any word access Writing the counter LSB resets the timer at FFFCh ST7 PERIPHERALS

Clearing a status bit is performed by a read access to the status register followed by an access (read or write) to the low byte of the corresponding register The alternate counter register is always matching the counter Use the alternate counter register when you do not want to clear the Timer Overflow Flag No interrupt is generated on compare when the PWM is active, but the ICF1 bit is set every period and can generates an interrupt Be aware that the implicit reading performed by the emulator might clear the status flags ST7 PERIPHERALS

Read CLR buffered CHR Any others Instructions ACLR buffered ACHR Returns the CLR buffered value CLR Clear TOF bit Returns the ACLR buffered value ACLR Reset counter to FFFCh Write CLR ACLR Clear TOF bit ST7 PERIPHERALS

Timer Configuration Example
Fill the Timer registers in order to generate a real time clock at 5ms using an interrupt strategy & a timer clock at 1µs (fCPU = 8MHz). An interrupt is generated every 5ms using Output compare1. OCMP1 pin has to be toggled every period What is the value to add to the TAOC1HR & TAOC1LR every period? ICIE OCIE TOIE FOLVL2 FOLVL1 OLVL2 IEDG1 OLVL1 TACR1 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXED TACR2 ST7 PERIPHERALS

Serial Peripheral Interface
Optional features : AD converter 16-bit Timer 8-bit Auto Reload Timer SPI SCI I2C EEPROM Programmable OpAmp CAN Optional ST623x BLOCK DIAGRAM Peripheral PORT 16-bit timer Power Supply Watchdog Timer Data Ram 256 bytes Oscillator Reset Test/Vpp INT Program Otp / Rom Interrupt Controller 8-Bit CORE SP PCH Accu Index X Index Y CC Data EEprom PCL ST7 PERIPHERALS

ST7 SPI Overview THE SPI CELL ALLOWS A FULL DUPLEX SYNCHRONOUS SERIAL COMMUNICATION BETWEEN 2 DEVICES MAIN FEATURE : Full duplex, 3 wire synchronous transfers Master : 6 frequency available. It rates up to 2 MHz Slave mode : it rates up 4 MHz THE CLOCK IS PROGRAMMABLE : POLARITY AND PHASE 3 DIFFERENT STATUS FLAG : Data transfer : data transfer completed Write collision : access to SPIDR during a transmission Fault flag : fault in master mode detected ST7 PERIPHERALS

ST7 SPI Master-Slave communication
SPI Clock Generator 8-bit Shift Register Master Slave MISO MOSI SCK SS 5V ST7 PERIPHERALS

SERIAL CLOCK GENERATOR
ST7 SPI Block diagram SPIDR Read Internal Bus Read Buffer IT request MISO SPISR MOSI 8-Bit Shift Register SPIF WCOL - MODF - - - - Write SPI STATE CONTROL SCK MASTER CONTROL SPICR MISCR2 SPIOD SSM SSI SPIE SPE SPR2- MSTR CPOL CPHA SPR1 SPR0 SERIAL CLOCK GENERATOR SS ST7 PERIPHERALS

ST7 SPI Single master configuration
SS SS SS SS SCK SCK SCK SCK Slave Slave Slave Slave MCU MCU MCU MCU MOSI MISO MOSI MISO MOSI MISO MOSI MISO MOSI MISO SCK P o r t s Master MCU 5V SS ST7 PERIPHERALS

SPI Configuration Example
Fill the SPICR register in order to configure the SPI cell in Master mode Serial clock at 5OOKHz (fCPU=8MHz) Sampling on 2nd edge High level after clock signal No interrupt generation SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0 SPICR ST7 PERIPHERALS

ST7 I2C Optional features : I2C AD converter 16-bit Timer

ST7 I2C Overview The I2C cell provides all I2C bus specific sequencing, protocol, arbitration and timing in order to reduce as much as possible the software overhead Polling Management or Interrupt Driven Cell Main feature : Multi Master capability Interrupt generation Standard I2C mode (up to 100kHz) and Fast I2C mode (up to 400kHz) 7-bit and 10-bit addressing ST7 PERIPHERALS

ST7 SCI Optional features : SCI AD converter 16-bit Timer

ST7 SCI Overview (1) Fcpu Ftx = [16 × PR × 2] × TR Frx =
FULL DUPLEX, ASYNCHRONOUS COMMUNICATION DUAL BAUD RATE GENERATOR (MAXIMUM SPEED FOR SCI TX and RX : 250kHz) PROGRAMMABLE WORD LENGTH 8 bits 9 bits (8 bits of data plus parity bit) RECEIVER WAKE FUNCTION BY THE MOST SIGNIFICANT BIT OR IDLE LINE Fcpu Ftx = [16 × PR × 2] × TR Frx = [16 × PR × 2] × RR ST7 PERIPHERALS

ST7 SCI Overview (2) 3 FLAGS
Buffer full Transmit buffer empty End of transmission MUTING FUNCTIONS FOR MULTIPROCESSOR CONFIGURATIONS NOISE, OVERRUN AND FRAME ERROR DETECTION 4 INTERRUPT SOURCES WITH FLAGS ST7 PERIPHERALS

ST7 SCI Serial data format
Start bit Stop bit Previous frame or idle line Optionnal parity bit 8 bit data LSB MSB Following frame or idle line ST7 PERIPHERALS

SCI Sampling Data Format
Data Sampled values Received bit value NF Flag 000 001 1 010 011 100 101 110 111 Bit Time Sampling Time Each bit time is Divided by 16 by the SCI clock Sampled 3 times on the 8th, 9th and 10th count of the SCI clock NF flag is set if the 3 sampling are not equal but the reception is still available ST7 PERIPHERALS

SCI Block Diagram fcpu / PR / 16 / 2 Transmit data register
Transmit shift register Receive data register Receive shift register Transmit Control Wake-Up Unit Receive Control Register 2 Status Register SCI Interrupt Transmit rate Control Receive rate Control fcpu / PR / 16 / 2 Control register 1 RDI pin TDO pin Data Register ST7 PERIPHERALS

ST7 SCI Clock selection f CPU ETPR ERPR BRR /2 /PR /16 ST7 PERIPHERALS
TRANSMITTER RECEIVER ETPR ERPR EXTENDED PRESCALER RECEIVER RATE CONTROL EXTENDED PRESCALER TRANSMITTER RATE CONTROL EXTENDED PRESCALER CLOCK RECEIVER RATE TRANSMITTER RATE BRR SCP1 f CPU CONTROL SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0 /2 /PR /16 CONVENTIONAL BAUD RATE GENERATOR EXTENDED RECEIVER PRESCALER REGISTER EXTENDED TRANSMITTER PRESCALER REGISTER ST7 PERIPHERALS

SCI Configurable Baud Rate
TR - SCT2:SCT0 RR - SCR2:SCR0 PR - SCP1,SCP0 ETPR /ERPR Baud Rate 300 1200 2400 4800 9600 3 - 01 10400 19000 X 13 38000 Values given for fCPU =8MHz PR selected by SCP1& SCP0 bits of SCIBRR Register TR selected by SCT2,SCT1 & SCT0 bits of SCIBRR Register RR selected by SCR2,SCR1 & SCR0 bits of SCIBRR Register Reach the industry standard requirement ST7 PERIPHERALS

SCI Configuration Example
WAKE SCICR1 Fill the SCI registers in order to configure the Sci cell in 8 Bit word reception at Bauds 8 bit word transmission at 1200 Bauds Interrupt generation when RDRF is set (reception flag) fCPU = 8MHz TIE TCIE RIE ILIE TE RE RWU SBK SCICR2 SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0 SCIBRR ST7 PERIPHERALS

ST7 EEPROM Data Optional features : EEPROM AD converter 16-bit Timer

SPGA Software Programable Gain Amplifier
Optional features : AD converter 16-bit Timer 8-bit Auto Reload Timer SPI SCI I2C EEPROM Programmable OpAmp CAN Optional ST623x BLOCK DIAGRAM Peripheral PORT 16-bit timer Power Supply Watchdog Timer Data Ram 256 bytes Oscillator Reset Test/Vpp INT Program Otp / Rom Interrupt Controller 8-Bit CORE SP PCH Accu Index X Index Y CC Data EEprom PCL ST7 PERIPHERALS

Programmable OpAmp OVERVIEW
Integrated RAIL to RAIL OpAmp Internal low programmable Gain (Up to 16) Integrated reference voltage sources, VCC dependent & independent (Band-Gap). OpAmp Outputs internally connected to ADC input Interupt flag in comparator mode Power on/off bit & active in low power modes DAC capability with PWM/ART output ST7 PERIPHERALS

digital (Comparator) output
SPGA Block Diagram SPGA1 Programmable gain Op-Amp To ADC Channel 8 Reference voltages: *1.2V, Vcc independant *8 steps, VCC dependant Analog (Amplifier ) or digital (Comparator) output ST7 PERIPHERALS

SPGA MODES (1) ST7 PERIPHERALS

OPAMP MODES (2) ST7 PERIPHERALS

SPGA MODES (3) ST7 PERIPHERALS

ST7 CAN Optional features : Programmable OpAmp CAN AD converter
16-bit Timer 8-bit Auto Reload Timer SPI SCI I2C EEPROM Programmable OpAmp CAN Optional ST623x BLOCK DIAGRAM Peripheral PORT 16-bit timer Power Supply Watchdog Timer Data Ram 256 bytes Oscillator Reset Test/Vpp INT Program Otp / Rom Interrupt Controller 8-Bit CORE SP PCH Accu Index X Index Y CC Data EEprom PCL ST7 PERIPHERALS

ST7 MICROCONTROLLER TRAINING

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