Presentation is loading. Please wait.

Presentation is loading. Please wait.

1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain.

Published by Modified over 9 years ago

Similar presentations

Presentation on theme: "1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain."— Presentation transcript:

1 1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain

2 2 Outline ► Synthesis of Asynchronous Controllers (overview) ► Structural approach for state encoding ► Experimental results ► Conclusions

3 3 This work Synthesis of Async. Controllers HDL Graph Model Logic Gates Physical Implementation CSP, Tangram, Balsa, Verilog… Petri nets, Automata, … Complex gates, two-level, … CMOS, FPGAs, …

4 4 Synthesis of Async. Controllers a b x y c y- a+b+ x+y+ c+ c- a- b- x- x+y- y+x- synthesis Signal Transition Graph y- a+b+ x+y+ c+ c- a- b- x- x+y- y+x-

5 5 Device LDS LDTACK D DSr DSw DTACK VME Bus Controller Data Transceiver Bus DSr LDS LDTACK D DTACK Read Cycle

6 6 DTACK- DSr+ LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK- DSw- DSw+ D+ LDS+ LDTACK+ D- DTACK+ read cycle write cycle

7 7 DTACK- DSr+ LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK- DSw+ D+ LDS+ LDTACK+ D- DTACK+ DSw- Specification ? DTACK D DSr LDS LDTACK csc synthesis Implementation

8 8 DTACK D DSr LDS LDTACK csc synthesis DSr+ DTACK- LDS- LDTACK- D- DSr- DTACK+ D+ LDTACK+ LDS+ State Graph (read cycle) DSr+ DTACK- LDS- LDTACK- D- DSr- DTACK+ D+ LDTACK+ LDS+ Encoded State Graph 10000 10010 10110 10111 11111 01111 01110 10110 01000 00000 DTACK- DSr+ LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK- DSw+ D+ LDS+ LDTACK+ D- DTACK+ DSw-

9 9 DSr+ DTACK- LDS- LDTACK- D- DSr- DTACK+ D+ LDTACK+ LDS+ 10000 10010 10110 10111 11111 01111 01110 10110 01000 The encoding problem 00000 LDS- LDTACK- LDS+ LDTACK+

10 10 DTACK D DSr LDS LDTACK csc synthesis DSr+ DTACK- LDS- LDTACK- D- DSr- DTACK+ D+ LDTACK+ LDS+ Encoded State Graph 10000 10010 10110 10111 11111 01111 01110 10110 01000 DSr+ DTACK- LDS- LDTACK- D- DSr- DTACK+ D+ LDTACK+ LDS+ Complete State Coding (CSC) csc - csc + DTACK- DSr+ LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK- DSw+ D+ LDS+ LDTACK+ D- DTACK+ DSw-

11 11 DTACK D DSr LDS LDTACK csc synthesis DSr+ DTACK- LDS- LDTACK- D- DSr- DTACK+ D+ LDTACK+ LDS+ Complete State Coding (CSC) csc - csc + Boolean equations: LDS = D  csc DTACK = D D = LDTACK csc = DSr Logic asynchronous circuit DTACK- DSr+ LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK- DSw+ D+ LDS+ LDTACK+ D- DTACK+ DSw-

12 12 DSr+ DTACK- LDS- LDTACK- D- DSr- DTACK+ D+ LDTACK+ LDS+ State Graph X 2X2X2X2X 101024 201048576 301073741824 401099511627776 501125899906842624 State space explosion problem DTACK- DSr+ LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK- DSw+ D+ LDS+ LDTACK+ D- DTACK+ DSw-

13 13 Event-based vs. State-based model Petri Net State Graph

14 14 Our approach to state encoding DSr+ DTACK- LDS- LDTACK- D- DSr- DTACK+ D+ LDTACK+ LDS+ DSr+ DTACK- LDS- LDTACK- D- DSr- DTACK+ D+ LDTACK+ LDS+ csc - csc + DTACK- DSr+ LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK- DSw+ D+ LDS+ LDTACK+ D- DTACK+ DSw- DTACK- DSr+ LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK- DSw+ D+ LDS+ LDTACK+ D- DTACK+ DSw- csc+ csc-

15 15 Outline ► Synthesis of Asynchronous Controllers (overview) ► Structural approach for state encoding:  Detection of conflicting states  Disambiguation by consistent signal insertion  Main algorithm for conflict resolution  MILP model to insert consistent signals ► Experimental results ► Conclusions

16 16 Detection of conflicting states DSr+DTACK- D- DSr- DTACK+ D+ LDS+ LDTACK+ ILP [Carmona & Cortadella, ICCAD’03] SAT-UNFOLD [Khomenko et al., Fund. Informaticae] LDS- LDTACK- DTACK- DSr+ LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK- DSw+ D+ LDS+ LDTACK+ D- DTACK+ DSw-

17 17 Disambiguation by consistent signal insertion DSr+DTACK- D- DSr- DTACK+ D+ LDS+ LDTACK+ LDS- LDTACK- STG Insertion of signal s must: 1.Solve conflict 2.Preserve consistency 3.Preserve persistency Disambiguate the conflicting states by introducing a new signal s: s+s- 10000 10010 10110 10111 01111 01110 10110 11111 10100 DTACK- DSr+ LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK- DSw+ D+ LDS+ LDTACK+ D- DTACK+ DSw- (CSC + consistency + persistency = SI-circuit)

18 18 Implicit place a+ b+ x- a- y+ x+y- b- DEF1 (Behavior): The behavior of the net does not depend on the place. DEF2 (Petri net): it never disables the firing of a transition. y+ a- x- a+ b+ x+ y- b-

19 19 Consistency y- b+ x- y+ x+x- b- Consecutive firings of a signal must alternate y+ x- y- b+ x- x+ b- y+... ?

20 20 Implicit Places & Consistency y- b+ x- y+ x+x- b- y=1 y=0 Theorem (Colom et al.) Places y=0 and y=1 are implicit if and only if signal y is consistent

21 21 Disambiguation by consistent signal insertion DSr+DTACK- D- DSr- DTACK+ D+ LDS+ LDTACK+ LDS- LDTACK- Disambiguate the conflicting states by introducing a new signal s: s+s- Insertion of s into the STG: s- will precede LDS+ s+ will precede DTACK- LDS+ s- ; LDS+

22 22 s+;DTACK- DSr+ s-;LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK- DSw- DSw+ D+ LDS+ LDTACK+ D- DTACK+ read cycle write cycle s=0 s=1 LDS+ DTACK-

23 23 s+;DTACK- DSr+ s-;LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK- DSw- DSw+ D+ LDS+ LDTACK+ D- DTACK+ read cycle write cycle s=0 s=1

24 24 s+;DTACK- DSr+ s-;LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK- DSw- DSw+ D+ LDS+ LDTACK+ D- DTACK+ read cycle write cycle s=0 s=1

25 25 s+;DTACK- DSr+ s-;LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK- DSw- DSw+ D+ LDS+ LDTACK+ D- DTACK+ read cycle write cycle s=0 s=1

26 26 s+;DTACK- DSr+ s-;LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK- DSw- DSw+ D+ LDS+ LDTACK+ D- DTACK+ read cycle write cycle s=0 s=1

27 27 s+;DTACK- DSr+ s-;LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK- DSw- DSw+ D+ LDS+ LDTACK+ D- DTACK+ read cycle write cycle s=0 s=1

28 28 s+;DTACK- DSr+ s-;LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK- DSw- DSw+ D+ LDS+ LDTACK+ D- DTACK+ read cycle write cycle s=0 s=1

29 29 s+;DTACK- DSr+ s-;LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK- DSw- DSw+ D+ LDS+ LDTACK+ D- DTACK+ read cycle write cycle s=0 s=1 s=0 is not implicit!! s is not consistent!!

30 30 s+;DTACK- DSr+ s-;LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK- DSw- DSw+ D+ LDS+ LDTACK+ D- DTACK+ read cycle write cycle s=0 s=1 s=0 is implicit s=1 is implicit s is consistent s-;D-

31 31 s+;DTACK- DSr+ s-;LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK- DSw- DSw+ D+ LDS+ LDTACK+ s-;D- DTACK+ read cycle write cycle s=0 s=1

32 32 s+ DSr+ s- LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK- DSw- DSw+ D+ LDS+ LDTACK+ s- DTACK+ read cycle write cycle LDS+ DTACK- D-

33 33 Main algorithm for solving CSC conflicts while CSC conflits exist do (σ 1,σ 2 ):= Find traces connecting conflict (s=0,s=1):= Find implicit places to break conflict Insert s+/s- transitions connected to (s=0) or (s=1) endwhile

34 34 ► Goal: avoid state enumeration to check implicitness of a place. ► Classical methods to avoid the explicit state space enumeration:  Linear Algebra (LP/MILP)  Graph Theory  Symbolic representation (BDDs)  Partiar order (Unfoldings) State space explosion problem Structural methods

35 35 Marking equation a+ a- b- b+ c+ c-b+ p1p1 p2p2 p3p3 p4p4 p5p5 p6p6 p7p7 a+ a- b+ b+ b- c+ c- p 1 -1 0 0 0 1 -1 0 p 2 1 0 -1 0 0 0 0 p 3 1 -1 0 0 0 0 0 p 4 0 0 0 0 0 1 -1 p 5 0 0 0 -1 0 1 0 p 6 0 0 1 0 -1 0 1 p 7 0 1 0 1 -1 0 0 Incidence matrix

36 36 1 0 Marking equation M’ = M + Ax = Necessary reachability condition, but not sufficient. 0 1 a+ a- b+ b+ b- c+ c- -1 0 0 0 1 -1 0 1 0 -1 0 0 0 0 1 -1 0 0 0 0 0 0 0 0 0 0 1 -1 0 0 0 -1 0 1 0 0 0 1 0 -1 0 1 0 1 0 1 -1 0 0 + 1 0 p1p2p3p4p5p6p7p1p2p3p4p5p6p7

37 37 LP model to check place implicitness LP formulation: M 0 + Ax = M M[P’] – F[P’,p]·s  0 M[p] – F[p,p]·s < 0 s·1 = 1 x, M, s  0 A place p is implicit if the following LP model is infeasible, where P’ = P – {p}: [Silva et al.] M0M0 M M :... P – {p}: p x

38 38 LP model to check place implicitness LP formulation: M 0 + Ax = M M[P’] – F[P’,p]·s  0 M[p] – F[p,p]·s < 0 s·1 = 1 x, M, s  0 A place p is implicit if the following LP model is infeasible, where P’ = P – {p}: [Silva et al.] LP formulation: min y · M 0 y·A[P’.T] ≤ A[p,T] y· F[P’, p] ≥ F[p, p] y≥ 0 DUAL A place p is implicit if M 0 [p] is greater than or equal to the optimal value of the following LP, where P’ = P – {p}:

39 39 MILP model to insert a implicit place A p A’ MILP variables: y, p MILP formulation: min y · M 0 y·A’[P’.T] ≤ A’[p,T] y· F’[P’, p] ≥ F[p, p] y≥ 0

40 40 MILP model to find insertion points that disambiguate the conflict MILP formulation: MILP “s=0 implicit” MILP “s=1 implicit” #( σ 1,s+) = #( σ 1,s-) + 1 #( σ 2,s-) = #( σ 2,s+) + 1 M 0 [s=0] + M 0 [s=1] = 1 DSr+DTACK- D- DSr- DTACK+ D+ LDS+ LDTACK+ LDS- LDTACK- If there is a solution, rows in A’ for s=0 and s=1 describe the insertion points (arcs in the net) σ1σ1 σ2σ2

41 41 Outline ► Synthesis of Asynchronous Controllers (overview) ► Structural approach for state encoding ► Experimental results ► Conclusions

42 42 Number of inserted encoding signals Benchmarks from [Cortadella et al., IEEE TCAD’97] petrify (state-based) MILP (structural)

43 43 Number of literals (area) Benchmarks from [Cortadella et al., IEEE TCAD’97] petrify (state-based) MILP (structural)

44 44 Experimental results: large controllers Synthesis with structural methods from [Carmona & Cortadella, ICCAD’03]

45 45 It doesn’t always work... Behaviorally equivalent

46 46 Conclusions ► First structural approach to state encoding for general STGs. ► Solutions comparable to state-based methods. ► Structural approach  can handle large controllers (few thousands of signals). ► May benefit from the well-structured specs obtained from HDLs.

Download ppt "1 State Encoding of Large Asynchronous Controllers Josep Carmona and Jordi Cortadella Universitat Politècnica de Catalunya Barcelona, Spain."

Similar presentations

Delay models (I) A B C Real (analog) behaviorAbstract behavior A B C Abstractions are necessary to define delay models manageable for design, synthesis.

Delay models (I) A B C Real (analog) behaviorAbstract behavior A B C Abstractions are necessary to define delay models manageable for design, synthesis.
Address comments to FPGA Area Reduction by Multi-Output Sequential Resynthesis Yu Hu 1, Victor Shih 2, Rupak Majumdar 2 and Lei He 1 1.

Address comments to FPGA Area Reduction by Multi-Output Sequential Resynthesis Yu Hu 1, Victor Shih 2, Rupak Majumdar 2 and Lei He 1 1.
Jorge Muñoz-Gama Josep Carmona

Jorge Muñoz-Gama Josep Carmona
26 September 2003U. Buy -- SEES 2003 Sidestepping verification complexity with supervisory control Ugo Buy Department of Computer Science Houshang Darabi.

26 September 2003U. Buy -- SEES 2003 Sidestepping verification complexity with supervisory control Ugo Buy Department of Computer Science Houshang Darabi.
1 BalsaOpt a tool for Balsa Synthesis Francisco Fernández-Nogueira, UPC (Spain) Josep Carmona, UPC (Spain)

1 BalsaOpt a tool for Balsa Synthesis Francisco Fernández-Nogueira, UPC (Spain) Josep Carmona, UPC (Spain)
1 Advanced Digital Design Synthesis of Control Circuits by A. Steininger and J. Lechner Vienna University of Technology.

1 Advanced Digital Design Synthesis of Control Circuits by A. Steininger and J. Lechner Vienna University of Technology.
Merged Processes of Petri nets Victor Khomenko Joint work with Alex Kondratyev, Maciej Koutny and Walter Vogler.

Merged Processes of Petri nets Victor Khomenko Joint work with Alex Kondratyev, Maciej Koutny and Walter Vogler.
Hazard-free logic synthesis and technology mapping I Jordi Cortadella Michael Kishinevsky Alex Kondratyev Luciano Lavagno Alex Yakovlev Univ. Politècnica.

Hazard-free logic synthesis and technology mapping I Jordi Cortadella Michael Kishinevsky Alex Kondratyev Luciano Lavagno Alex Yakovlev Univ. Politècnica.
Hardware and Petri nets Synthesis of asynchronous circuits from Signal Transition Graphs.

Hardware and Petri nets Synthesis of asynchronous circuits from Signal Transition Graphs.
Logic Decomposition of Asynchronous Circuits Using STG Unfoldings Victor Khomenko School of Computing Science, Newcastle University, UK.

Logic Decomposition of Asynchronous Circuits Using STG Unfoldings Victor Khomenko School of Computing Science, Newcastle University, UK.
Direct synthesis of large-scale asynchronous controllers using a Petri-net-based approach Ivan BlunnoPolitecnico di Torino Alex BystrovUniv. Newcastle.

Direct synthesis of large-scale asynchronous controllers using a Petri-net-based approach Ivan BlunnoPolitecnico di Torino Alex BystrovUniv. Newcastle.
Logic Synthesis for Asynchronous Circuits Based on Petri Net Unfoldings and Incremental SAT Victor Khomenko, Maciej Koutny, and Alex Yakovlev University.

Logic Synthesis for Asynchronous Circuits Based on Petri Net Unfoldings and Incremental SAT Victor Khomenko, Maciej Koutny, and Alex Yakovlev University.
Detecting State Coding Conflicts in STGs Using Integer Programming Victor Khomenko, Maciej Koutny, and Alex Yakovlev University of Newcastle upon Tyne.

Detecting State Coding Conflicts in STGs Using Integer Programming Victor Khomenko, Maciej Koutny, and Alex Yakovlev University of Newcastle upon Tyne.
Hardware and Petri nets: application to asynchronous circuit design Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel.

Hardware and Petri nets: application to asynchronous circuit design Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel.
Formal Verification of Safety Properties in Timed Circuits Marco A. Peña (Univ. Politècnica de Catalunya) Jordi Cortadella (Univ. Politècnica de Catalunya)

Formal Verification of Safety Properties in Timed Circuits Marco A. Peña (Univ. Politècnica de Catalunya) Jordi Cortadella (Univ. Politècnica de Catalunya)
Introduction to asynchronous circuit design: specification and synthesis Jordi Cortadella, Universitat Politècnica de Catalunya, Spain Michael Kishinevsky,

Introduction to asynchronous circuit design: specification and synthesis Jordi Cortadella, Universitat Politècnica de Catalunya, Spain Michael Kishinevsky,
Introduction to asynchronous circuit design: specification and synthesis Part IV: Synthesis from HDL Other synthesis paradigms.

Introduction to asynchronous circuit design: specification and synthesis Part IV: Synthesis from HDL Other synthesis paradigms.
Introduction to asynchronous circuit design: specification and synthesis Part III: Advanced topics on synthesis of control circuits from STGs.

Introduction to asynchronous circuit design: specification and synthesis Part III: Advanced topics on synthesis of control circuits from STGs.
1 Logic design of asynchronous circuits Part II: Logic synthesis from concurrent specifications.

1 Logic design of asynchronous circuits Part II: Logic synthesis from concurrent specifications.
Handshake protocols for de-synchronization I. Blunno, J. Cortadella, A. Kondratyev, L. Lavagno, K. Lwin and C. Sotiriou Politecnico di Torino, Italy Universitat.

Handshake protocols for de-synchronization I. Blunno, J. Cortadella, A. Kondratyev, L. Lavagno, K. Lwin and C. Sotiriou Politecnico di Torino, Italy Universitat.

Similar presentations

Ads by Google