1. ECE511: Digital System & Microprocessor
The M68000 Processor
ECE511: Digital System & Microprocessor

2. What we are going to learn in this session:
M68k hardware architecture:
M68k pin assignments
Pin functions.

3. The M68k Microprocessor M68000, M68k microprocessor.
Motorola Semiconductors, 1979.
16-bit processor, but can perform 32-bit operations.
Speed: 8-12 MHz.

4. The M68k Microprocessor Very advanced compared to 8-bit processors:
16-bit data bus, 24-bit address bus.
Can execute instructions twice as fast.
Still available today:
Simple, practical commands.
Robust: can be used for many applications.

5. The M68k Microprocessor

6. The M68k Microprocessor Has 64 pins: Power supply and clock (5 pins).
Processor status (3 pins).
6800 peripheral control (3 pins).
System control (3 pins).
Data bus (16 pins).
Address bus ( pins).
Asynchronous bus control (5 pins).
Bus arbitration control (3 pins).
Interrupt control (3 pins).

7. M68k Pin-Out 68000 CLK DTACK HALT RESET VPA BERR VMA E FC0 FC1 FC2 LDS
R/W
UDS AS
A1-A23
D0-D15
IPL0 BR BG
BGACK
IPL2
IPL1
+5V
GND
VCC
68000
Processor Status
6800 Peripheral
Control
System Control
Data Bus
Address Bus
Asynchronous
Bus Control
Bus Arbitration
Interrupt Control
M68k Pin-Out
*A0 is used inside 68k

8. Power Supply & Clock

9. 68000 CLK DTACK HALT RESET VPA BERR VMA E FC0 FC1 FC2 LDS R/W UDS AS
A1-A23
D0-D15
IPL0 BR BG
BGACK
IPL2
IPL1
+5V
GND
VCC
68000
Processor Status
6800 Peripheral
Control
System Control
Data Bus
Address Bus
Asynchronous
Bus Control
Bus Arbitration
Interrupt Control
*A0 is used inside 68k

10. Vcc & GND Vcc: GND: Voltage supply. Gives electrical power to 68k.
2 pins into M68k.
supplies 5V (±5%) voltage.
Connected to power supply.
GND:
Ground connection.
Lower potential for current flow.
2 pins out of M68k.

11. CLK Clock signal. 1 pin from timing circuit. Used for timing of:
Circuits connected to M68k.
Synchronous data transfer.
Asynchronous data transfer (less important).
50% duty cycle:
50% up, 50% down.
Fall-To-Rise, Rise-To-Fall = 10ns.
Slower devices use modified signal from CLK.

12. CLK Signal
CLK
50% up
50% down
10 ns
10 ns

13. Processor Status Pins

14. 68000 CLK DTACK HALT RESET VPA BERR VMA E FC0 FC1 FC2 LDS R/W UDS AS
A1-A23
D0-D15
IPL0 BR BG
BGACK
IPL2
IPL1
+5V
GND
VCC
68000
Processor Status
6800 Peripheral
Control
System Control
Data Bus
Address Bus
Asynchronous
Bus Control
Bus Arbitration
Interrupt Control
*A0 is used inside 68k

15. FC0, FC1, FC2 Function Code pins. 3 pins output.
Indicates type of cycle currently executing:
Operation on user program/data.
Operation on supervisor program/data.
Interrupt acknowledge.
Values assigned by M68k.
AS must be low for valid output.

16. Function Code Description
FC2
FC1
FC0 1
What the 68k is doing
Reserved (No meaning)
Acknowledging Interrupt Request
Accessing Supervisor Program
Accessing Supervisor Data
Accessing User Program
Accessing User Data AS X
Outputs not valid (AS is high).

17. FC to Protect Supervisor Memory
Address Bus
Data Bus

18. FC to Generate Interrupt Acknowledge Signal
68000
FC0
FC1
FC2 AS
Device
Requesting
Interrupt
INTACK

19. 6800 Peripheral Control

20. 68000 CLK DTACK HALT RESET VPA BERR VMA E FC0 FC1 FC2 LDS R/W UDS AS
A1-A23
D0-D15
IPL0 BR BG
BGACK
IPL2
IPL1
+5V
GND
VCC
68000
Processor Status
6800 Peripheral
Control
System Control
Data Bus
Address Bus
Asynchronous
Bus Control
Bus Arbitration
Interrupt Control
*A0 is used inside 68k

21. 6800 Peripheral Control
Allows M68k to interface with devices using older processors (M6800).
“Backward-Compatible.”
Three pins:
E: Clock
VMA: Valid Memory Address.
VPA: Valid Peripheral Address.

22. Synchronous Data Exchange
Mode where:
Data exchange performed using same timing.
Timing generated by single clock signal.
Shared by all synchronous devices.

23. E – 6800 Timing Signal Synchronizes data transfer – M68k & 6800:
Shared timing signal for slower 6800 devices.
Generated by M68k (output).
Modified CLK signal (/10).
40% duty cycle.
40% up, 60% down.

24. Timing Signals: E vs. CLK
6 CLK cycles
4 CLK cycles
After modified by M68k
*Therefore, E has 40% duty cycle

25. VPA – Valid Peripheral Address
Input pin: received from 6800 device.
Functions:
Generates confirmation response to M68k.
Tells M68k that device exists and ready.
To tell M68k to synchronize to E.

26. VMA – Valid Memory Address
Output pin: sent by M68k to 6800 device.
Functions:
Informs the device that M68k is ready for data transfer.
To tell 6800 device that M68k is sync. with E.

27. How M68k Accesses 6800 Devices1
M68k accesses device by
referring to device’s memory address. 2
Device detects attempt,
responds by setting
VPA to low. 3
After receiving VPA, M68k knows that
it has addressed a valid device.

28. How M68k Accesses 6800 Devices4
M68k stops synchronizing with CLK,
and starts synchronizing with E. 6
Device receives VMA,
knows M68k is ready. 7
Both parties begin data transfer. 5
M68k activates VMA to inform
device that it has synchronized with E.

29. How 6800 Peripheral Control Works
M68k outputs device address on Address Bus.
M68k pulls AS low.
Two possible outcomes:
If device doesn’t exist, M68k begins exception processing.
If device exists, device responds using VPA.
M68k receives signal:
Sync. with E
Pulls VMA low – ready to begin transfer.
Data transfer begins.

30. System Control

31. 68000 CLK DTACK HALT RESET VPA BERR VMA E FC0 FC1 FC2 LDS R/W UDS AS
A1-A23
D0-D15
IPL0 BR BG
BGACK
IPL2
IPL1
+5V
GND
VCC
68000
Processor Status
6800 Peripheral
Control
System Control
Data Bus
Address Bus
Asynchronous
Bus Control
Bus Arbitration
Interrupt Control
*A0 is used inside 68k

32. System Control
Responsible for control during catastrophic system faults.
Consists of three pins (1 input, 2 bi-directional):
RESET: Reset pin.
HALT: Halt pin.
BERR: Bus error pin.
Functions:
To receive error notifications.
Stop/reset M68k operations.
Stop/reset peripherals.

33. BERR – Bus Error Receives information of bus error.
From watchdog circuit.
Only informs M68k, doesn’t do anything else.
One-directional: into M68k.
Possible causes:
Invalid memory address.
Physical damage to bus.
Peripheral error.

34. HALT – Halt Signal Causes M68k to pause from executing instructions.
If active:
M68k stops execution after current cycle.
Waits until HALT is inactive.
Resumes execution.
Is bi-directional:
From external circuit / M68k (STOP command).
Both have same effect.
Also used to restart M68k (together with RESET).

35. RESET – Reset Signal Resets M68k / external circuit.
Is bi-directional:
If signal from external circuit, resets M68k (together with HALT for 10 clock cycles).
If signal from M68k, resets external circuitry connected to RESET pin (RESET instruction).

36. How M68k Manages Bus Errors
Watchdog Circuit 1
M68k executes current
processing cycle. 2
Watchdog detects problems
during execution, tells
M68k by activating BERR. 3
M68k receives BERR signal,
knows something is wrong. 4
M68k checks the status of HALT.

37. Cancel the problem bus cycle, store all address, data, & control. 6
M68k
Start exception processing
Re-run current processing cycle 5
If HALT is inactive. 5
If HALT is active. 6
Cancel the problem bus cycle,
store all address, data, & control. 6
Cancel the problem bus cycle. 7
Set address & data bus to
high impedance state. 7
Start bus exception processing. 8
Wait until HALT is inactive. 9
Load previous address, data &
control codes, re-run
execution of problem cycle.

38. Interrupt Control

39. 68000 CLK DTACK HALT RESET VPA BERR VMA E FC0 FC1 FC2 LDS R/W UDS AS
A1-A23
D0-D15
IPL0 BR BG
BGACK
IPL2
IPL1
+5V
GND
VCC
68000
Processor Status
6800 Peripheral
Control
System Control
Data Bus
Address Bus
Asynchronous
Bus Control
Bus Arbitration
Interrupt Control
*A0 is used inside 68k

40. Interrupt Control Interrupt pins for M68k. Functions:
3 pins (input).
Functions:
Used by external circuit to request interrupt.
Used to prioritize M68k tasks.
Generated by external circuits:
Important tasks assigned higher interrupts.
7 levels: 0 (lowest) to 7 (highest).

41. Interrupt Control IPL2 IPL1 IPL0 Interrupt level 1 0 (No Interrupt) 66 5 4 3 2
7 (Highest, Non-maskable )

42. Interrupt Example M68k External Peripheral 1 M68k is executing
instructions normally. 2
External peripheral has
important task for M68k. 3
External peripheral asks for attention by outputting interrupt on IPL0, IPL1, IPL2. 4
M68k compares interrupt level to SR. T S I2 I1 I0 X N Z V C

43. M68k 5
If external interrupt
higher than current. 5
If external interrupt
lower than current. 6 6
Wait for higher-level
interrupt being handled.
Update interrupt bits,
save controls,
registers into stack. 7
Handle interrupt,
restore interrupt bits. 8
Restore controls, registers,
resume normal execution.

44. Bus Arbitration Control

45. 68000 CLK DTACK HALT RESET VPA BERR VMA E FC0 FC1 FC2 LDS R/W UDS AS
A1-A23
D0-D15
IPL0 BR BG
BGACK
IPL2
IPL1
+5V
GND
VCC
68000
Processor Status
6800 Peripheral
Control
System Control
Data Bus
Address Bus
Asynchronous
Bus Control
Bus Arbitration
Interrupt Control
*A0 is used inside 68k

46. Bus Arbitration Control
Carries signals that allow bus takeovers:
M68k releases bus control to external device.
Faster data transfer, multi-CPU architecture, less overhead.
M68k waits, then takes back bus control.
Lets external devices become bus masters:
Device must have own microcontroller.
Accesses other peripherals as if it was CPU.
Usually for DMA.

47. Example: Transferring Data from HDD (CPU as Bus Master)
Serial I/O
Interrupt
Circuit
System Bus
Memory
CPU
Timing
All components must go through CPU for to transfer data.

48. Example: Transferring Data from HDD (HDD µC as Bus Master)
Micro-
Controller
Serial I/O
Interrupt
Circuit
System Bus
Memory
CPU
Timing
Less CPU overhead, CPU can process instructions that don’t require bus.

49. BR – Bus Request Used by external circuit to request bus control.
Input to M68k, 1 pin.
Connected to Bus Request output on Alternate Bus Master (ABM).
Sends and waits for M68k response.

50. BG – Bus Grant Used by M68k to: Output from M68k, 1 pin.
Acknowledge bus request.
Tell device that it will release bus control.
Output from M68k, 1 pin.
Connected to Bus Grant input on ABM.
Sends and waits for ABM response.

51. BGACK – Bus Grant Acknowledge
Used by ABM to acknowledge bus control transfer.
1 pin, input to M68k.
Before BGACK, must fulfill these conditions:
BG active: M68k has given permission.
AS inactive: M68k not using bus.
DTACK inactive: No other device using bus.
BGACK inactive: No other ABM as bus master.
BGACK active until ABM releases control.

52. Example of Bus Takeover
M68k
HDD
2. HDD wants to
become Bus Master.
1. M68k is executing
instructions normally.
3. HDD requests to M68k
by activating BR and waits.
4. When M68k is ready to
release bus control, activates
BG.

53. Example of Bus Takeover
M68k
HDD
5. HDD receives BG, knows
that request granted.
6. HDD activates BGACK to
acknowledge.
7. M68k releases bus control to HDD.
8. HDD takes control of bus,
Releases BGACK when done.
9. M68k takes bus control
back, resumes execution normally.

54. Data & Address Bus

55. 68000 CLK DTACK HALT RESET VPA BERR VMA E FC0 FC1 FC2 LDS R/W UDS AS
A1-A23
D0-D15
IPL0 BR BG
BGACK
IPL2
IPL1
+5V
GND
VCC
68000
Processor Status
6800 Peripheral
Control
System Control
Data Bus
Address Bus
Asynchronous
Bus Control
Bus Arbitration
Interrupt Control
*A0 is used inside 68k

56. Data Bus Used for general-purpose data transfer.
16-bits (D0 to D15), bi-directional.
Can transfer word or byte data.
Also used to carry vector number during Interrupt Acknowledge Cycle.

57. Address Bus Used to carry address values.
23-bits (A1 – A23), one-directional.
A0 used internally, spurs UDS, LDS.
Able to address 16 MB of memory.

58. Asynchronous Bus Control

59. 68000 CLK DTACK HALT RESET VPA BERR VMA E FC0 FC1 FC2 LDS R/W UDS AS
A1-A23
D0-D15
IPL0 BR BG
BGACK
IPL2
IPL1
+5V
GND
VCC
68000
Processor Status
6800 Peripheral
Control
System Control
Data Bus
Address Bus
Asynchronous
Bus Control
Bus Arbitration
Interrupt Control
*A0 is used inside 68k

60. Asynchronous Bus Control Group
Responsible for asynchronous data transfer.
Most common data transfer method.
5 pins:
Regulate data transfer: AS, DTACK.
Activate device: UDS, LDS.
Type of operation: R/W.

61. Asynchronous Transfer
Used to perform asynchronous data transfer:
Doesn’t follow strict timing from CLK.
Transfer based on “handshaking” between sender and receiver:
CLK replaced by sender-ready and receiver-ready.
Sender sends data when its ready.
Receiver sends signal when transfer completes.

62. AS – Address Strobe Purpose: Activated when M68k wants to use bus:
Indicates M68k using bus.
Valid address on address bus.
Activated when M68k wants to use bus:
Begin reading from memory.
Begin writing to memory.
Access peripherals.

63. R/W Used to specify read/write operation. 1 pin, output. Three states:
High (1): read (default).
Low (0): write.
High-impedance: when ABS is controlling bus.

64. DTACK – Data Transfer Acknowledge
Indicates device ready to begin data transfer.
Generated by external device being accessed.
When M68k receives signal, knows data transfer can be started, begins read/write.
During data transfer, M68k inserts wait states until DTACK is received.

65. UDS/LDS Used to activate correct memory chip during read/write:
Data usually stored in pairs of chips.
Each chip partially connected to data bus.
LDS activates D0 to D7 (odd bytes).
UDS activates D8 to D15 (even bytes).

66. How Data is Stored in Memory
$000000
$000000
$000002
$000004
$000006
(even
addresses)
$FFFFFE
$000001
$000003
$000005
$000007
(odd
$FFFFFF
Chip #1
Chip #2
Controlled
by UDS.
by LDS.
$000001
$000002
$000003
$000004
$000005 … …
$FFFFFE
$FFFFFF

67. How Data is Stored in Memory
MOVE.L #$ ,$1000 1 2 3 4 5 6 7 8
Chip #1
Chip #2
$1000
$12
$1001
$34
$1002
$56
$1003
$78
$1004 …
$1005 …
$1006 …
$1007 …
$1006 …
$1009 …
$1006 …
$100A …
* Controlled by UDS
* Controlled by LDS

68. How Data is Stored in Memory
$000000
Chip #1
Chip #2
Chip #3
Chip #4
$000001
$000000
$000002
$000004
$000006
$000FFE
$000001
$000003
$000005
$000007
$000FFF
$001000
$001002
$001004
$001006
$001FFE
$001001
$001003
$001005
$001007
$001FFF
$000002
$000003
$000004
EVEN
ODD
EVEN
ODD
$000005 … …
$001FFE
Controlled
by LDS.
Controlled
by UDS.
$001FFF

69. Activating the Correct Chip
Each memory chip has:
Data pins: outputs/receives to/from M68k.
Address pins: receives address from M68k.
OE (Output Enable): Allows data to be sent from chip.
CS (Chip Select): Enables chip for data transfer.
WE (Write Enable) (for RAM only): Allows data to be written to chip.

70. Activating the Correct Chip
Chip activated only if:
CS is enabled.
OE is enabled.
CS enabled when MAD receives unique pattern from Address Bus, AS active.
OE enabled when UDS or LDS active.

71. Address Bus Memory Address Decoder D0 D1 D2 OE D3 WE R/W D4 CS D5 D6
UDS OE D3 WE
R/W D4 CS D5 D6
Memory
Address
Decoder D7 D0 D1 AS D2 CS D3
R/W WE D4
LDS OE D5 D6 D7

72. Which one gets selected?
UDS
LDS CS
What data to access
Chip selected 1
No valid data
None
D8-D15 (even bytes)
Chip #1
D0-D7 (odd bytes)
Chip #2
D0-D15 (word data)
Both X
None (CS high)
* Correct your notes!

73. Read Cycle

74. M68k Read Cycle CLK A1 – A23 AS LDS/UDS R/W DTACK D0 – D15 FC0 – FC2

75. Step 1: Update FC & Specify Operation
CLK
A1 – A23 AS
LDS/UDS
R/W
DTACK
D0 – D15
FC0 – FC2
Read operation specified, R/W = 1.
FC0
FC1
FC2
Type of bus cycle 1
Accessing user data 1
Accessing User Program 1
Accessing SV Data 1
Accessing SV Program
FC0-2 informs what type of cycle is executing.

76. Step 2: Load Address Bus with Memory Address
CLK
A1 – A23 AS
LDS/UDS
R/W
DTACK
D0 – D15
FC0 – FC2
Just loaded, not sent yet.

77. Step 3: Specify Byte & Activate AS
CLK
A1 – A23 AS
LDS/UDS
R/W
DTACK
D0 – D15
FC0 – FC2
Indicates M68k using bus,
send address to MAD. Wait
for MAD response.
Specifies which data to access.
UDS
LDS
What data to access 1
No valid data
D8-D15 (even bytes)
D0-D7 (odd bytes)
D0-D15 (word data)
* Waits for DTACK

78. Step 4: Activate DTACK If address exists, external device
CLK
A1 – A23 AS
LDS/UDS
R/W
DTACK
D0 – D15
FC0 – FC2
If address exists, external device
activates DTACK.

79. Step 5: Get Data Memory puts data on data bus, loaded into M68k. CLK
A1 – A23 AS
LDS/UDS
R/W
DTACK
D0 – D15
FC0 – FC2
Memory puts data on data bus,
loaded into M68k.

80. Step 6: Complete Transfer
CLK
A1 – A23 AS
LDS/UDS
R/W
DTACK
D0 – D15
FC0 – FC2
When M68k done,
all controls returned
to normal. New
cycle starts.

81. Write Cycle

82. M68k Write Cycle CLK A1 – A23 AS LDS/UDS R/W DTACK D0 – D15 FC0 – FC2

83. Step 1: Specify Operation
CLK
A1 – A23 AS
LDS/UDS
R/W
FC0
FC1
FC2
Type of bus cycle 1
Accessing user data
DTACK 1
Accessing User Program 1
Accessing SV Data
D0 – D15 1
Accessing SV Program
FC0 – FC2
FC0-2 informs what type of cycle is executing.

84. Step 2: Load Address Bus M68k loads destination
CLK
A1 – A23 AS
M68k loads destination
address into address bus.
LDS/UDS
R/W
DTACK
D0 – D15
FC0 – FC2

85. Step 3: Activate AS, Specify Operation
CLK
AS = 0, Tells other devices that:
- M68k using bus now.
- Valid address on bus.
A1 – A23 AS
LDS/UDS
R/W
DTACK
D0 – D15
R/W = 0, write operation.
FC0 – FC2

86. Step 4: Load Data Bus Just loaded, not sent yet. CLK A1 – A23 AS
LDS/UDS
R/W
DTACK
D0 – D15
Just loaded, not sent yet.
FC0 – FC2

87. Step 5: Load Data Bus 2. M68k tells which chip to write on.
CLK
UDS
LDS
What data to access 1
No valid data
D8-D15 (even bytes)
D0-D7 (odd bytes)
D0-D15 (word data)
A1 – A23 AS
2. M68k tells which
chip to write on.
LDS/UDS
R/W
DTACK
1. Memory gives response,
address exists.
D0 – D15
3. Data bus contents
written to memory.
FC0 – FC2

88. Step 6: Load Data Bus New cycle starts. CLK A1 – A23 AS
When M68k done,
all controls returned
to normal.
LDS/UDS
R/W
DTACK
D0 – D15
FC0 – FC2
New cycle starts.

89. Conclusion

90. Summary of M68k Pins Group Function Pins Power & Clock
Provides power, clock signal.
Vcc, GND, CLK
Processor Status
Indicates type of cycle
being executed.
FC0 – FC2
6800 Peripheral
Control
Interfaces with older 6800
devices (synchronous transfer).
VPA, VMA, E
System Control
Error monitoring & handling.
BERR, RESET, HALT

91. Summary of M68k Pins Group Function Pins Interrupt Control
Interrupt request
by external device.
IPL0, IPL1, IPL2
Bus Arbitration
Control
Allows bus takeovers by ABM.
BR, BG, BGACK
Asynchronous
Bus Control
Allows asynchronous data transfer
between M68k and devices.
AS, R/W, UDS,
LDS, DTACK
Address Bus
Carries address from M68k.
A1-A23
Data Bus
Carries data from M68k & devices.
D0-D15

92. Please read: Antonakos, pg. 238-254
The End
Please read:
Antonakos, pg