1. 11/8/2004EE 42 fall 2004 lecture 291 Lecture #29 CMOS fabrication, clocked and latched circuits Last lecture: PMOS –Physical structure –CMOS –Dynamic circuits (Ring oscillators) This lecture: –CMOS fabrication –Clocked and latched circuits

2. 11/8/2004EE 42 fall 2004 lecture 292 CMOS PARAMETERS 3 generations of CMOS Return

3. 11/8/2004EE 42 fall 2004 lecture 293 Interconnect layers On top of the transistor layers, many metal layers interconnect the logic Illustration Actual TEM photo

4. 11/8/2004EE 42 fall 2004 lecture 294 MOS Fabrication and LAYOUT Thick oxide on silicon Thin oxide Gate (over oxide) Drain contact Source contact Device dimensions are larger than gate dimensions Gate Length = L Gate Width = W L W

5. 11/8/2004EE 42 fall 2004 lecture 295 Integrated Circuit Fabrication Goal: Mass fabrication (i.e. simultaneous fabrication) of hundreds of “Chips”, each a circuit (such as a microprocessor or memory chip) containing millions of transistors Method: Lay down thin films of semiconductors, metals and insulators and pattern each layer with a process much like printing (lithography). Minimum set of materials in an integrated circuit Si substrate SiO 2 insulator Polysilicon gate Metal contacts and wiring Other materials generally used (but not discussed here) Tungsten metal, Silicon nitride insulator, TiN and TiSi conductor regions

6. 11/8/2004EE 42 fall 2004 lecture 296 Patterning the Layers - Lithography Scheme: Subtractive Patterning … that means for example deposit a uniform film of Aluminum and then selectively remove it (etch it away) where you don’t want it. Process for applying the pattern: Photolithography How Photolithography works: –Coat the the uniform film to be etched with a photosensitive material –Expose the photosensitive material with a “picture” of the desired pattern (much like photographic printing) –Develop away the exposed areas –Use the resulting pattern to mask the etching of the underlying film. Goal: Transfer the desired pattern information to the wafer (for example the geometry of a wire)

7. 11/8/2004EE 42 fall 2004 lecture 297 Exposure Process A glass mask with a black/clear pattern is used to expose a wafer coated with about 1  m of photoresist (image projected with optical system) Mask Lens Image of mask will appear here We will shine UV light onto mask Si wafer photoresist oxide

8. 11/8/2004EE 42 fall 2004 lecture 298 Review Exposure Process A glass mask with a black/clear pattern is used to expose a wafer coated with about 1  m of photoresist Areas exposed to UV light are susceptible to being chemically removed (developed) Mask Lens Image of mask will appear here (3 dark areas, 4 light areas) photoresist wafer oxide UV light

9. 11/8/2004EE 42 fall 2004 lecture 299 Photoresist Development and Etching Solutions with high pH dissolve the areas exposed to UV; unexposed areas (under the black patterns) are not dissolved oxide layer After etching the oxide After developing the photoresist Developed photoresist oxide layer Exposed areas of photoresist oxide layer

10. 11/8/2004EE 42 fall 2004 lecture 2910 CMOS oxide P-Si n-well ppnn G D G D S S

11. 11/8/2004EE 42 fall 2004 lecture 2911 Basic CMOS Inverter Inverter IN OUT V DD p-ch V DD OUT IN n-ch CMOS Inverter Example layout of CMOS Inverter

12. 11/8/2004EE 42 fall 2004 lecture 2912 GROUND IN OUT V DD N-WELL NMOS Gate PMOS Gate Al “wires”

13. 11/8/2004EE 42 fall 2004 lecture 2913 Data Synchronization problem Combinatorial logic gates can give incorrect answers prematurely and may take several gate propagation delays produce an answer. Clocks (signals as to when to proceed) and latches (which capture and hold the correct outputs) can provide synchronization.

14. 11/8/2004EE 42 fall 2004 lecture 2914 Combinatorial vs Sequential logic In the digital circuits we have created so far, the output was a function only of the instantaneous inputs. –combinational logic circuits. If the action of circuits depends on the history of the inputs, or on past operations, they are –sequential logic circuits.

15. 11/8/2004EE 42 fall 2004 lecture 2915 Combinatorial A combinatorial circuit can be schematically represented as a black box, and is completely described by a truth table of the outputs as a function of the current inputs

16. 11/8/2004EE 42 fall 2004 lecture 2916 dynamic circuit the output is a function not only of the current inputs, but of the internal state of the circuits, residual from previous inputs. The circuit can not be described by a truth table of the inputs only. ABCABC Outputs

17. 11/8/2004EE 42 fall 2004 lecture 2917 Ring oscillator as an example of a dynamic circuit V out STAGE 1 V DD STAGE 101 At at time equal to exactly 1001 gate delays, the input to stage 1 will go high, and after another equal time it will go low, etc. This is a “RING OSCILLATOR”, which toggles at a frequency equal to 1/(1001  delay ). Such ring oscillators are commonly used to estimate the performance of a technology. No switch is actually needed, the output is permanently wired to the input, and the oscillations start when power is applied.

18. 11/8/2004EE 42 fall 2004 lecture 2918 Unpredictability of dynamic circuits In the case of the ring oscillator, the output just oscillates forever without regard to its inputs. If there are many different paths and possible delays, the output of the circuit can be highly unpredictable or chaotic, because just what may happen at an instant in time can depend on the exact value of all the previous delays.

19. 11/8/2004EE 42 fall 2004 lecture 2919 Representing a Discrete Sequence in Continuous Time From our viewpoint, time appears to be a continuous variable. For a digital sequence, we want discrete values [x0,!x1, x2, x3, …], not a continuous function x(t). The typical way to handle this is to use a clock. The continuous sequence is “sampled” at regularly spaced times, when the clock “ticks”.

20. 11/8/2004EE 42 fall 2004 lecture 2920 Making time discrete The most common answer to this complexity is the same one we used for simplifying circuits before, but this now we make time discrete. Rather than letting all of the internal nodes take logical states at arbitrary times, we use latches to prevent the change of state of some nodes until a specific time.

21. 11/8/2004EE 42 fall 2004 lecture 2921 sequential circuit In a sequential circuit, the circuit can be described by a truth table as a function of the inputs and the values held byf internal latches. ABCABC Outputs

22. 11/8/2004EE 42 fall 2004 lecture 2922 Dynamic Latch To synchronize the data, L remains low until the data is correct. When L goes high the inverse of the data is passed. Note that in a dynamic latch, the old value is just held by the capacitance, which works in CMOS because of the low leakage of the switches, and the fact that the next gate consumes no current. When L is low, the voltage at the output is left floating C OUT V DD V OUT V IN

23. 11/8/2004EE 42 fall 2004 lecture 2923 Latches A latch remembers one bit, either a 0 or 1. The bit is held while the latch is low, until the next time the latch is high. Each time the latch line pulses, whatever value (0 or 1) exists at the flip-flop’s input is remembered; the old value is lost. While the latch is high, the output will follow the input

24. 11/8/2004EE 42 fall 2004 lecture 2924 Feedback Can Provide Memory Q Q H H L L H H Feed back between gates can form a circuit with static memory. This kind of circuit is called a flip-flop

25. 11/8/2004EE 42 fall 2004 lecture 2925 the Opposite State Q Q H H L H H L

26. 11/8/2004EE 42 fall 2004 lecture 2926 Set/Reset Q Q S R

27. 11/8/2004EE 42 fall 2004 lecture 2927 Set/Reset flip-flop This circuit will do the following 1.If S=0 and R=0, Q will not change, but will remember its former value. 2.If S=1 and R=0, then Q=1 3.If S=0 and R=1, then Q=0 4.S=1 and R=1 is an illegal combination

28. 11/8/2004EE 42 fall 2004 lecture 2928 Set/Reset flip-flop with clock S R Q Q φ

29. 11/8/2004EE 42 fall 2004 lecture 2929 sequential circuit In a dynamic circuit with latches, we still have a race when a latch passes a value, of its output feeds back to its input. ABCABC Outputs

30. 11/8/2004EE 42 fall 2004 lecture 2930 Two phase latches If we put two latches into every feedback path, and make sure both latches are never open at the same time, we can insure predicable results. ABCABC Outputs

31. 11/8/2004EE 42 fall 2004 lecture 2931 Asynchronous vs. clocked logic One straightforward way of making sure that the behavior is predictable, and does exactly what it was designed to do, is to latch all of the circuits in the block by one signal, which is called a clock. If a dynamic circuit is built without a clock, it is called asynchronous logic. It is possible to build fast, low power asynchronous circuits, but difficult to make complex systems which behave correctly

32. 11/8/2004EE 42 fall 2004 lecture 2932 Clocked logic If we put two latches into every feedback path, and make sure both latches are never open at the same time, we can insure predicable results. ABCABC Outputs