1. Silicon Programming--Intro. to HDLs1 Hardware description languages: introduction intellectual property (IP) introduction to VHDL and Verilog entities and architectural bodies behavioral and structural views examples

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5. 5 Two main HDLs: VHDL / Verilog VHDL--Very High Speed Integrated Circuit (VHSIC) Hardware Description Language Standards--IEEE 1076-1987;1076-1993; Ada-like language Additions--VHDL-AMS--Analog & Mixed Signal Verilog—1985; proprietary to Cadence until 1990 (“open Verilog”) C-like language Additions—Verilog-AMS—Analog & Mixed Signal NOTE: this course is NOT designed to make you a VHDL or Verilog expert! The Altera tools (as well as other synthesis tools) work best with simpler HDL constructs (e.g., structural representations, modeest levels of nesting)

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10. 10 Note: keywords, comment, “entity” syntax

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14. Silicon Programming--Intro. to HDLs14 Full adder example:

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25. Silicon Programming--Intro. to HDLs25 Verilog: The following is taken from the introduction by Dan Hyde at: http://www.eg.bucknell.edu/~cs320/1995-fall/verilog-manual.html Other references can be found at: http://www.verilog.net/docs.html Architectural, behavioral, gate, and switch levels supported Gate level: logic elements (structural) Switch level: transistor level Verilog program can be used for design, simulation, synthesis Basic construct: module Verilog program consists of interconnected modules Usually a “top” module encapsulates all the others

26. Silicon Programming--Intro. to HDLs26 Some simple examples of combinational logic: // NAND gate (behavioral model) module NAND(in1, in2, out); input in1, in2; output out; assign out = ~(in1 & in2); endmodule //AND gate (structural module) module AND(in1, in2, out); input in1, in2; output out; wire w1; NAND NAND1(in1, in2, w1); NAND NAND2(w1, w1, out); endmodule

27. Silicon Programming--Intro. to HDLs27 A simple sequential logic example—what does it do? (Note “control statements” initial and always—these will run concurrently) module simple; reg [0:7] A, B; reg C; //stop execution after 20 time steps initial begin: stop_at // Will stop the execution after 20 simulation units. #20; $stop; end //so these statements at time 0 A = 0; $monitor(" %0d %b %b %b", $time, A, B, C); end //main_process will loop until simulation is over (#1 means do at each step) always begin: main_process #1 A = A + 1; #1 B[0:3] = ~A[4:7]; #1 C = &A[6:7]; end endmodule

28. Silicon Programming--Intro. to HDLs28 Assignment: Default is that new assignment is made whenever inputs change: assign out = ~( in1 & in2) Blocking and nonblocking statements: Blocking: =; works like a “regular” programming language; Nonblocking: <=; does all right-hand assignment simultaneously module blocking; reg [0:7] A, B; initial begin: init1 A = 3; #1 A = A + 1; B = A + 1; $display("Blocking: A= %b B= %b", A, B ); A = 3; #1 A <= A + 1; B <= A + 1; #1 $display("Non-blocking: A= %b B= %b", A, B ); end endmodule output: Blocking: A= 00000100 B= 00000101 Non-blocking: A= 00000100 B= 00000100

29. Silicon Programming--Intro. to HDLs29 Tasks and functions Verilog has tasks, which are like procedures (do not return a value) Verilog also has functions, which must execute and return a value in 1 time step A task can invoke a function; a function cannot invoke a task Example: module tasks; task add; input a, b; output c; reg R; begin R = 1; if (a == b) c = 1 & R; else c = 0; end endtask initial begin: init1 reg p; add(1, 0, p); //invoke the task $display("p= %b", p); end endmodule (A similar function can also be defined)

30. Silicon Programming--Intro. to HDLs30 Timing: Like VHDL, Verilog uses discrete event simulation The following can advance timing (order of events may not be predictable): 1.gate or wire delay, if specified. 2. a delay control, introduced by the # symbol. 3. an event control, introduced by the @ symbol. 4. the wait statement.

31. Silicon Programming--Intro. to HDLs31 Examples: Delay control: #10: A = A + 1; //delay 10 units before executing the assignment Event control: @r begin // controlled by any value change in reg r A = B&C; end @(posedge clock2) A = B&C; // controlled by positive edge of clock2 @(negedge clock3) A = B&C; // controlled by negative edge of clock3 forever @(negedge clock) begin A = B&C; end

32. Silicon Programming--Intro. to HDLs32 Control by a specific event: @(event6) begin end To trigger the event: -> event6 Wait statement: wait until condition becomes true (level sensitive): wait (A == 3) begin A = B&C; end

33. Silicon Programming--Intro. to HDLs33 Fork / join: allow multiple threads Example: fork: three begin // code for thread 1 end begin // code for thread 2 end begin // code for thread 3 end join All 3 threads execute concurrently; when all are finished, jump to statement after “join”