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Activation Records (Introduction) Mooly Sagiv html://www.math.tau.ac.il/~msagiv/courses/wcc03.html Chapter 6.3.

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Presentation on theme: "Activation Records (Introduction) Mooly Sagiv html://www.math.tau.ac.il/~msagiv/courses/wcc03.html Chapter 6.3."— Presentation transcript:

1 Activation Records (Introduction) Mooly Sagiv html://www.math.tau.ac.il/~msagiv/courses/wcc03.html Chapter 6.3

2 Outline What is the problem? A possible structure of the activation records A simple stack machine Example compilation

3 The problem The compiler needs to allocate memory for variables Consistent with program semantics –Scope –Duration –Recursion Efficient (moderate runtime cost) Solution?

4 Typical Virtual Memory Content Lower addresses static area Stack area Heap area

5 A Typical Stack Frame

6 Basic Compiler Phases

7 void main() { printf(“%d\n”, fact(3)); } int fact(int n) { if (n==0) return 1; else return n * fact(n-1) ; } Example Program

8 void main() { printf(“%d\n”, fact(3)); } Activation Record for main (before fact) Administrative part 3 SP FP

9 void main() { printf(“%d\n”, fact(3)); } Activation Record for main (after fact) Administrative part 3 6 SP FP

10 void main() { printf(“%d\n”, fact(3)); } Activation Record for main (before printf) Administrative part 6 x87 SP FP x87 “%d\n”

11 Stack Instructions InstructionActions Push_Const cstack[--SP]=c Push_Local istack[--SP]=stack[FP+i] Store_Local istack[FP+i]=stack[SP++] Add_Top2stack[SP+1]+=stack[SP++] Sub_Top2stack[SP+1]-=stack[SP++] Mul_Top2stack[SP+1]*=stack[SP++] Branch LPC = L; Branch_Eq LT1= stack[SP++]; T2 = stack[SP++]; if (T1==T2) PC =L JSR Lstack[--SP] = FP; stack[--SP] = PC; FP=SP-1;PC =L RTST= stack[SP++]; PC=stack[SP++]; FP=stack[SP++]; stack[--SP]=T WPopStack[SP+1] = Stack[SP]

12 void main() { printf(“%d\n”, fact(3)); }.global _main L1: Push_Const 3 Push_Const 0 JSR _fact WPop Push_Const L2 JSR _printf.data L2 : “%d\n”.end Code Generated for main

13 Activation Record for fact Administrative part SP FP int fact(int n) { if (n==0) return 1; else return n * fact(n-1) ; } n 3 ret FP+5 0

14 Code generated for fact int fact(int n) { if (n==0) return 1; else return n * fact(n-1) ; } L4: Push_Constant 1 RTS. global _fact L3: Push_Local 5 Push_Const 0 Branch_Eq L4 Branch L5 L5: Push_Local 5 Push_Local 5 Push_Const 1 Subtr_Top 2 Push_Const 0 JSR _fact WPop Mult_Top2 RTS.end

15 Execution of fact Administrative part FP n 3 ret FP+5 L3: Push_Local 5 Push_Const 0 Branch_Eq L4 Branch L5 L4: Push_Constant 1 RTS L5: Push_Local 5 Push_Local 5 Push_Const 1 Subtr_Top 2 Push_Const 0 JSR _fact WPop Mult_Top2 RTS main SP 0

16 Execution of fact Administrative part FP n 3 ret FP+5 L3: Push_Local 5 Push_Const 0 Branch_Eq L4 Branch L5 L4: Push_Constant 1 RTS L5: Push_Local 5 Push_Local 5 Push_Const 1 Subtr_Top 2 Push_Const 0 JSR _fact WPop Mult_Top2 RTS main SP 3 0

17 Execution of fact Administrative part FP n 3 ret FP+5 L3: Push_Local 5 Push_Const 0 Branch_Eq L4 Branch L5 L4: Push_Constant 1 RTS L5: Push_Local 5 Push_Local 5 Push_Const 1 Subtr_Top 2 Push_Const 0 JSR _fact WPop Mult_Top2 RTS main SP 3 0 0

18 Execution of fact Administrative part FP n 3 ret FP+5 L3: Push_Local 5 Push_Const 0 Branch_Eq L4 Branch L5 L4: Push_Constant 1 RTS L5: Push_Local 5 Push_Local 5 Push_Const 1 Subtr_Top 2 Push_Const 0 JSR _fact WPop Mult_Top2 RTS main SP 0

19 Execution of fact Administrative part FP n 3 ret FP+5 L3: Push_Local 5 Push_Const 0 Branch_Eq L4 Branch L5 L4: Push_Constant 1 RTS L5: Push_Local 5 Push_Local 5 Push_Const 1 Subtr_Top 2 Push_Const 0 JSR _fact WPop Mult_Top2 RTS main SP 0

20 Execution of fact Administrative part FP n 3 ret FP+5 L3: Push_Local 5 Push_Const 0 Branch_Eq L4 Branch L5 L4: Push_Constant 1 RTS L5: Push_Local 5 Push_Local 5 Push_Const 1 Subtr_Top 2 Push_Const 0 JSR _fact WPop Mult_Top2 RTS main SP 3 0

21 Execution of fact Administrative part FP n 3 ret FP+5 L3: Push_Local 5 Push_Const 0 Branch_Eq L4 Branch L5 L4: Push_Constant 1 RTS L5: Push_Local 5 Push_Local 5 Push_Const 1 Subtr_Top 2 Push_Const 0 JSR _fact WPop Mult_Top2 RTS main 3 SP 3 0

22 Execution of fact Administrative part FP n 3 ret FP+5 L3: Push_Local 5 Push_Const 0 Branch_Eq L4 Branch L5 L4: Push_Constant 1 RTS L5: Push_Local 5 Push_Local 5 Push_Const 1 Subtr_Top 2 Push_Const 0 JSR _fact WPop Mult_Top2 RTS main 3 3 SP 1 0

23 Execution of fact Administrative part FP n 3 ret FP+5 L3: Push_Local 5 Push_Const 0 Branch_Eq L4 Branch L5 L4: Push_Constant 1 RTS L5: Push_Local 5 Push_Local 5 Push_Const 1 Subtr_Top 2 Push_Const 0 JSR _fact WPop Mult_Top2 RTS main 3 2 SP 0

24 Execution of fact Administrative part FP n 3 ret FP+5 L3: Push_Local 5 Push_Const 0 Branch_Eq L4 Branch L5 L4: Push_Constant 1 RTS L5: Push_Local 5 Push_Local 5 Push_Const 1 Subtr_Top 2 Push_Const 0 JSR _fact WPop Mult_Top2 RTS main 3 2 SP 0 0

25 FP L3: Push_Local 5 Push_Const 0 Branch_Eq L4 Branch L5 L4: Push_Constant 1 RTS L5: Push_Local 5 Push_Local 5 Push_Const 1 Subtr_Top 2 Push_Const 0 JSR _fact WPop Mult_Top2 RTS main SP Administrative part n ret 3 3 Administrative part n ret 2 2 n 1 0 0 0

26 FP L3: Push_Local 5 Push_Const 0 Branch_Eq L4 Branch L5 L4: Push_Constant 1 RTS L5: Push_Local 5 Push_Local 5 Push_Const 1 Subtr_Top 2 Push_Const 0 JSR _fact WPop Mult_Top2 RTS main SP Administrative part n ret 3 3 Administrative part n ret 2 2 Administrative part 0 n ret 1 1 0 0 0

27 FP L3: Push_Local 5 Push_Const 0 Branch_Eq L4 Branch L5 L4: Push_Constant 1 RTS L5: Push_Local 5 Push_Local 5 Push_Const 1 Subtr_Top 2 Push_Const 0 JSR _fact WPop Mult_Top2 RTS main SP Administrative part n ret 3 3 Administrative part n ret 2 2 Administrative part n ret 1 1 Administrative part n ret 0 1 0 0 0

28 FP L3: Push_Local 5 Push_Const 0 Branch_Eq L4 Branch L5 L4: Push_Constant 1 RTS L5: Push_Local 5 Push_Local 5 Push_Const 1 Subtr_Top 2 Push_Const 0 JSR _fact WPop Mult_Top2 RTS main SP Administrative part n ret 3 3 Administrative part n ret 2 2 Administrative part 0 1 n ret 1 1 0 0 0

29 FP L3: Push_Local 5 Push_Const 0 Branch_Eq L4 Branch L5 L4: Push_Constant 1 RTS L5: Push_Local 5 Push_Local 5 Push_Const 1 Subtr_Top 2 JSR _fact Push_Const 0 WPop Mult_Top2 RTS main Administrative part n ret 3 3 Administrative part n ret 2 2 Administrative part 1 n ret 1 1 SP 0 0

30 FP L3: Push_Local 5 Push_Const 0 Branch_Eq L4 Branch L5 L4: Push_Constant 1 RTS L5: Push_Local 5 Push_Local 5 Push_Const 1 Subtr_Top 2 Push_Const 0 JSR _fact WPop Mult_Top2 RTS main Administrative part n ret 3 3 Administrative part n ret 2 2 Administrative part n ret 1 1 SP 0 0

31 FP L3: Push_Local 5 Push_Const 0 Branch_Eq L4 Branch L5 L4: Push_Constant 1 RTS L5: Push_Local 5 Push_Local 5 Push_Const 1 Subtr_Top 2 Push_Const 0 JSR _fact WPop Mult_Top2 RTS main Administrative part n ret 3 3 Administrative part n ret 2 2 n 1111 SP 0 0

32 FP L3: Push_Local 5 Push_Const 0 Branch_Eq L4 Branch L5 L4: Push_Constant 1 RTS L5: Push_Local 5 Push_Local 5 Push_Const 1 Subtr_Top 2 Push_Const 0 JSR _fact WPop Mult_Top2 RTS main Administrative part n ret 3 3 Administrative part n ret 2 2 n 1 SP 0 0

33 FP L3: Push_Local 5 Push_Const 0 Branch_Eq L4 Branch L5 L4: Push_Constant 1 RTS L5: Push_Local 5 Push_Local 5 Push_Const 1 Subtr_Top 2 Push_Const 0 JSR _fact WPop Mult_Top2 RTS main Administrative part n ret 3 3 Administrative part n ret 2 2 SP 0 0

34 FP L3: Push_Local 5 Push_Const 0 Branch_Eq L4 Branch L5 L4: Push_Constant 1 RTS L5: Push_Local 5 Push_Local 5 Push_Const 1 Subtr_Top 2 Push_Const 0 JSR _fact WPop Mult_Top2 RTS main Administrative part n ret 3 3 n 2222 SP 0

35 FP L3: Push_Local 5 Push_Const 0 Branch_Eq L4 Branch L5 L4: Push_Constant 1 RTS L5: Push_Local 5 Push_Local 5 Push_Const 1 Subtr_Top 2 Push_Const 0 JSR _fact WPop Mult_Top2 RTS main Administrative part n ret 3 3 2 SP 0

36 FP L3: Push_Local 5 Push_Const 0 Branch_Eq L4 Branch L5 L4: Push_Constant 1 RTS L5: Push_Local 5 Push_Local 5 Push_Const 1 Subtr_Top 2 Push_Const 0 JSR _fact WPop Mult_Top2 RTS main Administrative part n ret 3 6 SP 0

37 FP main n ret 3 6 SP L1: Push_Const 3 Push_Const 0 JSR _fact WPop Push_Const L2 JSR _printf

38 FP main 6 SP L1: Push_Const 3 Push_Const 0 JSR _fact WPop Push_Const L2 JSR _printf

39 FP main 6 SP L1: Push_Const 3 Push_Const 0 JSR _fact WPop Push_Const L2 JSR _printf x87

40 main 6 _printf x87 FP Administrative part SP x87

41 Code For Register Machine

42 Register Instructions InstructionActions Load_Const c, RiRi=c Load_Local c(Ri), RjRj=*(Ri+c) Store_Local Ri, c(Rj)*(Rj+c)=Ri Add_Constant c, RiRi = Ri+c Add_Reg Ri, RjRj = Rj+Ri Sub_Constant Ri, cRi = Ri - c Sub_Reg Ri, RjRj =Rj-Ri CMP Ri, RjCC = Ri -Rj CMP_Const C, RiCC = Ri - C Branch LPC = L; Branch_EQ Lif (CC==EQ) PC =L JSR L*(--SP) = FP; *(--SP) = PC; FP=SP-1;PC =L RTSPC=*(SP++); FP=*(SP++)

43 void main() { printf(“%d\n”, fact(3)); }. global _main Add_Constant -K1, SP L1: Load_Const 3, R0 JSR _fact Load_Reg R0, R1 Load_Const L2, R0 JSR _printf Add_Constant K1, SP RTS.data L2 : “%d\n”.end Register Code Generated for main

44 Register Code generated for fact int fact(int n) { if (n==0) return 1; else return n * fact(n-1) ; } L4: Load_Constant 1, R0 Goto L6.global _fact Add _Constant -K2, SP L3: Cmp_Constant R0, 0 Branch_Eq L4 Branch L5 L5: Store_Local R0, 5(FP) Sub_Constant 1, R0 JSR _fact Load_Local 5(FP), R1 Mult_Reg R1, R0 Goto L6 L6: Add_Constant K2, SP RTS.end

45 Summary Activation records is a runtime data structure Updated by code generated by the compiler Support from machine instruction

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