1. Sprinkler Buddy Presentation #7: “Redesign of Adder Parts And Layout of Other Major Blocks” 3/07/2007 Team M3 Kalyan Kommineni Kartik Murthy Panchalam Ramanujan Sasidhar Uppuluri Devesh Nema Design Manager: Bowei Gai “Low Cost Irrigation Management For Everyone ! ”

2. Current Status Determine Project Develop Project Specifications Plan Architectural Design Determination of all components in design Detailed logical flowchart Design a Floor Plan Create Structural Verilog Make Transistor Level Schematic Layout (~65% done with all big modules except FP Add passing LVS …) Testing (Extraction, LVS, and Analog Sim.) (ongoing…)

3. Last Week’s Floor Plan

4. Current Floor Plan

5. Transistor Count … Block (# used)Old TCNew TC 40:20 Muxes (6)362 60:20 Muxes (2)644 Counter (2)220 KC ROM (1)1256 P ROM (1)122 Metric Storage SRAMS (2) 2430 Constant Storage ROM (1) 428 Floating Point Adder (4) 3210 3977 Floating Point Multiplier (2) 1398 1026 10 Bit Registers (9) 210 Datapath Logic / Misc. 2305 Total: 32,921

6. Updated Design Size Block (# used)Size (um) 40:20 Muxes (4)20 x 80 60:20 Muxes (2)20 x 120 Counter (2)12 x 17 KC ROM (4 parts)181 x 8 P ROM (1)70 x 8 Metric Storage SRAMS (2) 181 x 60 Constant Storage ROM (1) 181 x 8 Floating Point Adder (4) 96x151 Floating Point Multiplier (2) 89 x 40 10 Bit Registers (8)50 x 10 441um x 411 um ~ 1 : 1.07 aspect ratio.181 mm^2 area

7. Layout: Progress Everything laid out has density >.3 transistors/um 2 All Big Modules LVS FP Add is the exception Had to redo many components Initial layout was too big and messed up the floor plan Currently done with all components except new shifter New layouts enable us to match initial size estimate

8. Layout : Muxes 1 bit 6 bit Density:.42 transistors/um 2

9. Layout : Registers 10 bits Density:.40 transistors/um 2 1 bit

10. Layout : Register Enable Custom “AND” Gate

11. Layout : “Is Zero?” Unit Density:.41 transistors/um 2 Sideways Inverters Split NAND Gate

12. Layout : Leading Zero Counter Density:.40 transistors/um 2

13. Layout : Conditional Add/Sub Density:.30 transistors/um 2

14. Layout : Subtract Density:.33 transistors/um 2

15. Layout : New Barrel Shifter Still needs decoder and input buffers

16. Layout : FP Add Exponent Unit Density:.34 transistors/um 2 Inputs Outputs

17. Layout : FP Add Sig. Unit Density:.30 transistors/um 2 Inputs Outputs There is some wiring left and the shifter must be inserted

18. Layout : FP Adder Density:.33 transistors/um 2 Needs to be wired

19. Layout : Redone Integer Multiply So, why did we leave a HUGE hole? Density:.32 transistors/um 2

20. Layout : Floating Point Multiply Density:.31 transistors/um 2 InputsOutputs

21. Design Challenges and Implementation Decisions For The Past Week Design Challenge Translation to HW Low Power Design Although we tried to get make extremely compact layouts we were cognizant of power We didn’t make sacrifices such as long poly lines which could have yielded more compressed layout

22. Problems/Questions We cannot accurately lay out our control logic until the FP Adder is done and global layout is all positioned

23. For Next Time Lots and Lots more Layout Finish the FP Adder Place all blocks into global layout and fit control logic into the gaps Global routing