1. An Introduction to Synopsys Design Automation Jeremy Lee jslee@engr.uconn.edu November 7, 2007

2. Introduction  Why the need CAD tools?  Time to market decreasing (< a year)  Designs are becoming more complex (System-on-a-chip)  Synopsys is one of many EDA vendors vying for designer mind- share

3. Introduction (cont.)  Why do we (in academia) need CAD tools?  Keep our research relevant to industry  Know what needs improving (academia on cutting edge)

4. What will be covered?  Overview of tools What’s available? What do the tools do?  Example Flow  Will not be a step-by-step how-to.

5. Getting Synopsys Started at UConn  Synopsys Linux binaries are available on the ECS fileserver: /apps/ecs-apps/software/synopsys  Releases: Y-2006, Z-2007  bashrc and cshrc files located at /apps/ecs-apps/software/synopsys/etc  Synopsys directory can be mounted directly using NFS files:/ApplicationDirectories/nfs/ecs- apps/software/synopsys  Tools are location dependent Must be in same directory structure as on server  Gui or console modes

6. Synopsys Galaxy Platform at UConn (Y-2006) Design Compiler JupiterXT Astro Physical Compiler Design Automation PrimeTime SI/PX/VX PrimePower Star-RCXT Formality VCS Nanosim HSpice Sign-off / Validation / Verification DFT Compiler DFT MAX TetraMAX Design for Test

7. Design Automation  Design Compiler RTL to gate-level synthesis  Physical Compiler Layout-aware RTL to gate-level synthesis  JupiterXT Floorplanning tool  Astro Placement and routing

8. Design Compiler (DC)  Synthesizes gate level netlists from RTL-level  Optimizes netlists Removes unused or redundant logic Tie-off nets that are constant  Requires standard cell library timing characterization  Attempts to meet timing and area constraints (SDC File)

9. Libraries  Supposed to be provided by fab  Gates in standard cell library  Operating condition corners Gate delays  Wire load models Compensates delay for fan-out

10. SDC File  Synopsys Design Constraints (SDC)  Set up clock period  Specifies timing and area requirements that are to be met during mapping and optimization

11. SDC Constraints Input Delay Output Delay Driving Cell Load

12. DC Flow Read Netlist Map to Link Library (if gate-level) Apply Constraints Netlist Write-out Optimized Netlist SDC Cons. Map to Target Library and Optimize Read Libraries

13. JupiterXT  Floorplanning Power/Ground Network Planning Pin/Power pad placement Blockages Memory placement  Performed through GUI or command line

14. Astro  Placement and routing tool  Requires physical information of standard cell library (provided by fab) Graphic Data System (GDSII) Library Exchange Format (LEF)  Physical design in multiple formats GSDII Design Exchange Format (DEF)

15. Astro Flow Import Netlist and Constraints Netlist Open Libraries Read/Setup Floorplan Run Placement Routing Physical Design SDC Cons.

16. Synopsys Galaxy Platform at UConn (Y-2006) Design Compiler JupiterXT Astro Physical Compiler Design Automation PrimeTime SI/PX/VX PrimePower Star-RCXT Formality VCS Nanosim HSpice Sign-off / Validation / Verification DFT Compiler DFT MAX TetraMAX Design for Test

17. Sign-off/Validation/Verification  Formality Verify netlist  PrimeTime SI/PX/VX Timing validation (signal-integrity, power-aware, variation-aware)  PrimePower Power validation

18. Sign-off/Validation/Verification (cont.)  Star-RCXT Extraction tool  VCS HDL simulator  NanoSim HDL simulator w/ parasitics  HSpice Spice simulator

19. PrimeTime SI/PX/VX (PT-SI/PX/VX)  Calculates and reports path delays  Verify operating frequency after logic synthesis  Can be back-annotated with extracted parasitics for post-layout verification

20. PT-SI/PX/VX Flow Read Netlist Map to Link Library (if gate-level) Apply Constraints Netlist SDC Cons. Read Libraries Back-annotate design Report Timing results Meet spec? ECO Next phase Yes No Parasitics Process Variation *New*

21. Putting the Pieces Together RTL Netlist SDC Cons. Logic Synthesis Gate Netlist Logic Libraries Sign-off Fails Passes Physical Synthesis Physical Libraries Layout Extraction Sign-off Fails Passes To Fab

22. Synopsys Galaxy Platform at UConn (Y-2006) Design Compiler JupiterXT Astro Physical Compiler Design Automation PrimeTime SI/PX/VX PrimePower Star-RCXT Formality VCS Nanosim HSpice Sign-off / Validation / Verification DFT Compiler DFT MAX TetraMAX Design for Test

23.  DFT Compiler Scan chain insertion  DFT Max Test compression tool  TetraMax Automatic test pattern generation (ATPG)

24. Additional Reading  Synopsys Website www.synopsys.com  Documentation Synopsys OnLine Documenation (SOLD) Available on any of the UConn ECS Linux servers  Electronic Synopsys Users Group (ESNUG) www.deepchip.com