1. 1 Lucas-Lehmer Primality Tester Presentation 11 April 24th 2006 Team: W-4 Nathan Stohs W4-1 Brian Johnson W4-2 Joe Hurley W4-3 Marques Johnson W4-4 Design Manager: Prateek Goenka Overall Objective: Modular Arithmetic unit with a creative use

2. 2 Status Finished –Project Chosen –C simulations –Behavioral Verilog –Structural Verilog –Floor Plan –Schematics –Pathmill Simulation of Top Level –Module Layout –Global Layout In Progress –Global Simulations

3. 3 Final Floorplan

4. 4 Floorplan

5. 5 Poly Layer Mask

6. 6 Metal1 Layer Mask

7. 7 Metal2 Layer Mask

8. 8 Metal3 Layer Mask

9. 9 Metal4 Layer Mask

10. 10 compare Propagation Delay

11. 11 partial_product Propagation Delay

12. 12 Propagation Delays ModuleSchematicextractedRC FSM80ps270ps mod_p769ps944ps mod_add817ps907ps partial_product -shift_left -shift_right -sub_16 1.11ns 780ps 779ps 144ps - 964ps 976ps 167ps count645ps954ps compare727ps2.25ns

13. 13 Power Estimates ModuleSchematicextractedRC FSM8.88uW11.72uW mod_p60.63uW77.80uW mod_add86.16uW89.75uW partial_product368uW- count53.81uW60.35uW compare131.1nW1.98uW

14. 14 Design Specifications ModuleTransistor Count Area (µm²) Transistor Density FSM1521,200.13 mod_p1,2808,603.15 mod_add1,1685,603.21 partial_product7,32854,680.13 count1,4128,320.17 sub_165762,934.20 Registers8966,028.15 compare40125.32 Total12,85286,704.15 Aspect Ratio 2.45 0.79 2.40 1.16 6.79 4.49 4.76 2.90 1.01

15. 15 What’s Next Simulations on Global Design

16. 16 Questions?