1. Embedded Architecture Description Language Qiang Liu School of Software, Tshinghua University Joint work with Juncao Li, Nick Pilkington, and Fei Xie Dept. of Computer Science, Portland State Univ.

2. 2 2 Agenda Problems Unified Component Model EADL EADL in Embedded System Dev. Conclusions and Future Work

3. 3 Problems Lack of architectural specification support for co-design –Hardware (or software) only –HW and SW in the same language Little consideration of verification and verification reuse –Not considered when defining embedded system architectures –Very limited verification reuse

4. 4 Our Contributions Embedded Architecture Description Language –Component-based architectures of both hardware and software –Flexible platform-oriented semantics instantiation –Design reuse and verification reuse Apply EADL to –Co-design –Co-verificaition –Co-simulation

5. 5 5 Agenda Problems Unified Component Model EADL EADL in Embedded System Dev. Conclusions and Future Work

6. 6 Unifying hardware and software component models Component = (Design, Interface, Properties) HW, SW, and bridge components –Different design and interface specification languages –Same property specification language Verified properties are associated with components Unified Component Model Software Component Software Component Software Component Bridge Component Bridge Component Hardware Component Hardware Component

7. 7 Bridge Components: Filling Semantics Gap Dual interfaces: hardware and software Bridge design –Abstracts processor, bus model, and embedded OS –Maps between HW and SW events –Is fully synthesizable –Supports both co-simulation and co-verification Software Component Bridge Component Hardware Component Interactions follow software semantics Interactions follow hardware semantics

8. 8 Transactional Bridge Spec Language Event mappings implemented by transactors interrupt ADC.INTR -> InterruptHPLADCC.IntrHPLADCC() 1; void outpadc (unsigned int val, unsigned int address) { ADC.PSEL=1; ADC.PADDR=address; ADC.PWDATA=val; ADC.PWRITE=1; @ (posedge ADC.PCLK); ADC.PENABLE=1; @ (posedge ADC.PCLK); ADC.PSEL=0; ADC.PENABLE=0; } unsigned int inpadc (unsigned int address){ ADC.PSEL=1; ADC.PADDR=address; ADC.PWRITE=0; @ (posedge ADC.PCLK); ADC.PENABLE=1; @ (posedge ADC.PCLK); ADC.PSEL=0; ADC.PENABLE=0; return ADC.PRDATA; } Transactor spec inherits from HW and SW languages C Verilog

9. 9 9 Environment of C (Components interacting with C ) Component Property A property of a component C is a pair (p, A(p)) –p is a temporal assertion –A(p) is a set of assumptions on environment of C –p is verified assuming A(p) holds. C p A(p)  p holds on C A(p) Assumptions = Assumed Properties

10. 10 Agenda Problems Unified Component Model EADL EADL in Embedded System Dev. Conclusions and Future Work

11. 11 Component-based semantics overlay –Complete architectural semantics –Incomplete execution and interface semantics Platform-oriented instantiation –Platform provides HW, SW, and BSL semantics –EADL supplies architectural semantics SW Semantics (NesC) Bridge Semantics (BSL) HW Semantics (Verilog) Embedded Architecture Description Language Embedded Architecture Description Lang.

12. 12 Key EADL Language Features EntitiesTemplates Port Service-oriented grouping of events Service provides-uses relationship Port Type Event co-relation similarity Component Unit of reuse Component interface based on ports Component Template Component external similarity Architecture Sub-components Sub-component inter-connections Architectural Pattern Component internal similarity

13. 13 VisualEADL: Tool Support for EADL

14. 14 An Architectural Pattern Example

15. 15 Entities – PropertiesTemplates – Property Templates Port Service-oriented grouping of events Service provides-uses relationship Port-level properties Port Type Event co-relation similarity Port-level property templates Component Units of reuse Component interface based on ports Component-level properties Component Template Component external similarity Component-level property templates Architecture Sub-components Sub-component inter-connections Architecture-level properties Architectural Pattern Component internal similarity Architecture-level property templates Architecture-Aware Property Specification

16. 16 Property Specification Tool Support

17. 17 Agenda Problems Unified Component Model EADL EADL in Embedded System Dev. Conclusions and Future Work

18. 18 Component-Based Co-Design Platform initialization (1)Analyze application domain (2)Define bridge spec. language (3)Identify architectural patterns (4)Identify reusable components (5)Verify components bottom-up Platform-oriented pattern-guided component-based co-design (1)Select architectural patterns (2)Partition system into comps. (3)Reuse components (4)Develop new components (5)Verify system top-down Platform extension (1)Identify new architectural patterns (2)Identify new reusable comps. (3)Create and verify larger reusable comps. bottom-up (4)Extend pattern and comp. libs A platform for embedded systems: Processors and buses Embedded OS HW, SW, and bridge spec. languages Library of reusable components Libraries of ports, component templates and architectural patterns

19. 19 Embedded System IDE (ESIDE)

20. 20 HDL Source Code NesC Source Code 20 Component-Based Co-Simulation SW Application Components Bridge Components (BSL) BSL Compiler SW Executable C Compiler C Code NesC Compiler SW Platform Components HW Application Components HW Platform Components Giano HW Executable HDL Compiler ModelSim PLI

21. 21 Tool Support for Transactional BSL SW Components (NesC) Bridge Components (BSL) HW Components (Verilog) Configuration BSL Compiler SW Executable C Compiler C Code NesC Compiler HW Executable Verilog Compiler Verilog Code Pre-Processor For verification – Direct compilation to formal languages For simulation and deployment – Indirect compilation

22. 22 Property formulation problems –What are the system properties to verify –What are the component properties needed –What are the environment assumptions Architecture-based property formulation and Reuse –Port –Component template –Architectural pattern Component-Based Co-Verification

23. 23 3-Tier Architectural Reuse in Co-Design Component Port Properties from Port Port Visible Variables Component Template Properties from Component template Properties from Architectural pattern; Decomposition strategies Sub- Component Architectural Pattern Problem addressed: property formulation and decomposition

24. 24 Co-Verification Tool Support

25. 25 Agenda Problems Unified Component Model EADL EADL in Embedded System Dev. Conclusions and Future Work

26. 26 Conclusions and Future Work Developed EADL –Component-based architectures of both hardware and software –Flexible platform-oriented semantics instantiation –Design reuse and verification reuse Demonstrated effectiveness in support to –Co-design, co-simulation and co-verification Future work –Other component properties rather than temporal correctness

27. 27 Further Information Website: –http://www.cs.pdx.edu/~xie/co-ver/co-ver-home.htmhttp://www.cs.pdx.edu/~xie/co-ver/co-ver-home.htm Email: –juncao@cs.pdx.edujuncao@cs.pdx.edu Questions?